Semiconductor device and electronic device

ABSTRACT

A semiconductor device with high design flexibility is provided. A first transistor and a second transistor having electrical characteristics different from those of the first transistor are provided over the same layer without significantly increasing the number of manufacturing steps. For example, semiconductor materials with different electron affinities are used for a semiconductor layer in which a channel of the first transistor is formed and a semiconductor layer in which a channel of the second transistor is formed. This allows the threshold voltages of the first transistor and the second transistor to differ from each other. Forming a gate electrode using a damascene process enables miniaturization and high density of the transistors. Furthermore, a highly-integrated semiconductor device is provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device and a driving method thereof. Another embodiment of the present invention relates to an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device (e.g., a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like may include a semiconductor device.

2. Description of the Related Art

A technique in which a transistor is formed using a semiconductor thin film has attracted attention. Such a transistor is used in a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film that can be used for a transistor. As another material, an oxide semiconductor has been attracting attention.

For example, a technique in which a transistor is manufactured using a zinc oxide or an In—Ga—Zn-based oxide as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

In addition, a technique in which oxide semiconductor layers with different electron affinities (or conduction band minimum states) are stacked to increase the carrier mobility of a transistor is disclosed (see Patent Documents 3 and 4).

In recent years, demand for an integrated circuit in which transistors and the like are integrated with high density has risen with reductions in the size and weight of an electronic device. In addition, the productivity of the semiconductor device including an integrated circuit is required to be improved.

REFERENCE Patent Document [Patent Document 1] Japanese Published Patent Application No. 2007-123861 [Patent Document 2] Japanese Published Patent Application No. 2007-096055 [Patent Document 3] Japanese Published Patent Application No. 2011-124360 [Patent Document 4] Japanese Published Patent Application No. 2011-138934 SUMMARY OF THE INVENTION

An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device that can be manufactured with high productivity.

Another object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long time. Another object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed data writing. Another object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. Another object of one embodiment of the present invention is to provide a low-power semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the descriptions of these objects do not disturb the existence of other objects. One embodiment of the present invention does not have to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

Providing transistors with different electrical characteristics in one semiconductor device can increase circuit design flexibility. On the other hand, the transistors need to be separately fabricated, resulting in a significant increase in the number of steps for manufacturing the semiconductor device. The significant increase in the number of manufacturing steps easily induces a decrease in yield; thus, productivity of the semiconductor device might be prominently reduced. According to one embodiment of the present invention, transistors having different electrical characteristics can be provided in one semiconductor device without significantly increasing the number of manufacturing steps.

One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes first to fourth electrodes, first to third semiconductor layers, first and second layers, and a second insulating layer. The second transistor includes fifth to eighth electrodes, fourth to eighth semiconductor layers, third and fourth layers, and a third insulating layer. The first insulating layer includes a region overlapping with the first electrode. The first semiconductor layer includes a region overlapping with the first insulating layer. The second semiconductor layer includes a region overlapping with the first semiconductor layer. The second semiconductor layer includes a region overlapping with the second electrode and a region overlapping with the third electrode. The first layer includes a region overlapping with the second electrode. The second layer includes a region overlapping with the third electrode. The third semiconductor layer includes a region overlapping with the second semiconductor layer. The second insulating layer includes a region overlapping with the third semiconductor layer. The fourth electrode includes a region overlapping with the second insulating layer. A side surface of the fourth electrode and the third semiconductor layer partly overlap with each other with the second insulating layer therebetween. The first electrode and the fourth electrode partly overlap with each other with the second semiconductor layer therebetween. The first insulating layer includes a region overlapping with the fifth electrode. The fourth semiconductor layer includes a region overlapping with the first insulating layer. The sixth semiconductor layer includes a region overlapping with the fourth semiconductor layer. The sixth electrode includes a region overlapping with the sixth semiconductor layer. The third layer includes a region overlapping with the sixth electrode. The fifth semiconductor layer includes a region overlapping with the first insulating layer. The seventh semiconductor layer includes a region overlapping with the fifth semiconductor layer. The seventh electrode includes a region overlapping with the seventh semiconductor layer. The fourth layer includes a region overlapping with the seventh electrode. The eighth semiconductor layer includes a region overlapping with the sixth semiconductor layer and a region overlapping with the seventh semiconductor layer. The third insulating layer includes a region overlapping with the eighth semiconductor layer. The eighth electrode includes a region overlapping with the third insulating layer. A side surface of the eighth electrode and the eighth semiconductor layer partly overlap with each other with the third insulating layer therebetween. The fifth electrode and the eighth electrode partly overlap with each other with the eighth semiconductor layer therebetween.

The first to fourth semiconductor layers each preferably include an oxide semiconductor. The first to eighth layers each preferably include an oxide semiconductor. At least one of the first electrode and the fourth electrode is capable of functioning as a gate electrode. At least one of the fifth electrode and the eighth electrode is capable of functioning as a gate electrode.

The second semiconductor layer is capable of functioning as a semiconductor layer in which a channel is formed. The eighth semiconductor layer is capable of functioning as a semiconductor layer in which a channel is formed.

The threshold voltage of the second transistor when the fifth electrode and the eighth electrode have the same potential is preferably higher than the threshold voltage of the first transistor when the first electrode and the fourth electrode have the same potential.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device that can be manufactured with high productivity can be provided.

According to one embodiment of the present invention, a semiconductor device capable of retaining data for a long time can be provided. According to one embodiment of the present invention, a semiconductor device capable of high-speed data writing can be provided. According to one embodiment of the present invention, a semiconductor device with high design flexibility can be provided. According to one embodiment of the present invention, low-power semiconductor device can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the descriptions of these effects do not disturb the existence of other effects. One embodiment of the present invention does not have to have all the effects listed above. Other effects will be apparent from and can be derived from the descriptions of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional view of a semiconductor device of one embodiment of the present invention and FIGS. 1B and 1C show the electrical characteristics of the semiconductor device.

FIGS. 2A to 2D illustrate a transistor of one embodiment of the present invention.

FIGS. 3A to 3C illustrate a transistor of one embodiment of the present invention.

FIGS. 4A and 4B show energy band diagrams of a transistor of one embodiment of the present invention.

FIG. 5 shows an energy band diagram of a transistor of one embodiment of the present invention.

FIGS. 6A to 6E illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 7A to 7D illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 8A to 8C illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 9A to 9C illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 10A to 10C illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 11A to 11C illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 12A to 12C illustrate semiconductor devices according to embodiments of the present invention.

FIGS. 13A to 13C illustrate semiconductor devices according to embodiments of the present invention.

FIGS. 14A to 14C illustrate semiconductor devices according to embodiments of the present invention.

FIG. 15A is a cross-sectional view of a semiconductor device of one embodiment of the present invention and FIGS. 15B and 15C show the electrical characteristics of the semiconductor device.

FIGS. 16A to 16C illustrate a transistor of one embodiment of the present invention.

FIGS. 17A to 17C illustrate a transistor of one embodiment of the present invention.

FIGS. 18A and 18B illustrate a method for manufacturing a transistor of one embodiment of the present invention.

FIGS. 19A to 19C illustrate semiconductor devices of embodiments of the present invention.

FIGS. 20A to 20C illustrate semiconductor devices of embodiments of the present invention.

FIGS. 21A and 21B illustrate semiconductor devices of embodiments of the present invention.

FIGS. 22A to 22C illustrate a semiconductor device of one embodiment of the present invention.

FIGS. 23A and 23B illustrate a semiconductor device of one embodiment of the present invention.

FIGS. 24A to 24C illustrate a semiconductor device of one embodiment of the present invention.

FIG. 25 illustrates a semiconductor device of one embodiment of the present invention.

FIGS. 26A to 26C are each a circuit diagram of a semiconductor device of one embodiment of the present invention.

FIGS. 27A to 27D are each a circuit diagram of a semiconductor device of one embodiment of the present invention.

FIGS. 28A and 28B are circuit diagrams of memory devices of embodiments of the present invention.

FIG. 29 illustrates a memory device of one embodiment of the present invention.

FIG. 30 is a block diagram showing a configuration example of a CPU.

FIG. 31 is a block diagram of an RF tag of one embodiment of the present invention.

FIGS. 32A to 32F illustrate application examples of an RF tag of one embodiment of the present invention.

FIGS. 33A and 33B illustrate a structure example of an imaging device.

FIG. 34 illustrates a configuration example of a peripheral circuit.

FIGS. 35A and 35B illustrate structure examples of an imaging device.

FIGS. 36A to 36C are each a circuit diagram illustrating an example of an imaging device.

FIG. 37 illustrates a structure example of an imaging device.

FIG. 38 illustrates a structure example of an imaging device.

FIGS. 39A and 39B are top views of a semiconductor wafer of one embodiment of the present invention.

FIG. 40A is a flowchart showing a manufacturing process example of an electronic component, and FIG. 40B is a schematic perspective view of the electronic component.

FIGS. 41A to 41C illustrate examples of a display device.

FIGS. 42A and 42B illustrate examples of a display device.

FIGS. 43A and 43B each illustrate a configuration example of a driver circuit.

FIGS. 44A to 44C illustrate examples of a display device.

FIGS. 45A and 45B illustrate examples of a display device.

FIG. 46 illustrates an example of a display module.

FIG. 47 illustrates electronic devices of one embodiment of the present invention.

FIGS. 48A to 48F each illustrate an electronic device of one embodiment of the present invention.

FIGS. 49A to 49C each illustrate the atomic ratio of an oxide of one embodiment of the present invention.

FIG. 50 shows the crystal structure of InMZnO₄.

FIGS. 51A to 51E show XRD structural analysis results of a CAAC-OS and a single crystal oxide semiconductor and selected-area electron diffraction patterns of a CAAC-OS.

FIGS. 52A to 52E show a cross-sectional TEM image and plan-view TEM images of a CAAC-OS and images obtained through analysis thereof.

FIGS. 53A to 53D show electron diffraction patterns and a cross-sectional TEM image of an nc-OS.

FIGS. 54A and 54B show cross-sectional TEM images of an a-like OS.

FIG. 55 is a graph showing changes in a crystal part of an In—Ga—Zn oxide induced by electron irradiation.

FIG. 56 is an energy band diagram of a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed.

FIG. 57 illustrates an example of a deposition apparatus.

FIGS. 58A to 58C illustrate an example of a deposition apparatus.

FIGS. 59A to 59C illustrate an example of a deposition apparatus.

FIGS. 60A to 60C illustrate Example.

FIGS. 61A to 61C illustrate Example.

FIGS. 62A to 62D illustrate Example.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments and Example will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments and Example. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated in some cases.

The position, size, range, and the like of each component illustrated in the drawings and the like are not accurately represented in some cases to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, and the like disclosed in the drawings and the like. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which is not illustrated in some cases for easy understanding.

Especially in a top view (also referred to as a “plan view”), a perspective view, or the like, some components might not be illustrated for easy understanding of the invention. In addition, some hidden lines and the like might not be shown.

Ordinal numbers such as “first” and “second” in this specification and the like are used in order to avoid confusion among components and do not denote the priority or the order such as the order of steps or the stacking order. A term without an ordinal number in this specification and the like might be provided with an ordinal number in a claim in order to avoid confusion among components. A term with an ordinal number in this specification and the like might be provided with a different ordinal number in a claim. A term with an ordinal number in this specification and the like might not be provided with an ordinal number in a claim and the like.

In addition, in this specification and the like, a term such as an “electrode” or a “wiring” does not limit the function of a component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Further, the term “electrode” or “wiring” can also mean a combination of a plurality of “electrodes” and “wirings” formed in an integrated manner.

Note that the term “over” or “under” in this specification and the like does not necessarily mean that a component is placed “directly above and in contact with” or “directly below and in contact with” another component. For example, the expression “electrode B over insulating layer A” does not necessarily mean that the electrode B is on and in direct contact with the insulating layer A and can mean the case where another component is provided between the insulating layer A and the electrode B.

Furthermore, functions of a source and a drain might be switched depending on operation conditions, e.g., when a transistor having a different polarity is employed or the direction of current flow is changed in circuit operation. Therefore, it is difficult to define which is the source (or the drain). Thus, the terms “source” and “drain” can be used to denote the drain and the source, respectively.

In this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without being limited to a predetermined connection relation, for example, a connection relation shown in drawings or text, another connection relation is included in the drawings or the text.

In this specification and the like, the term “electrically connected” includes the case where components are connected through an object having any electric function. There is no particular limitation on an “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Thus, even when the expression “electrically connected” is used, there is a case in which no physical connection is made and a wiring is just extended in an actual circuit.

Note that the channel length refers to, for example, a distance between a source (source region or source electrode) and a drain (drain region or drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in the top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not fixed to one value in some cases. Therefore, in this specification and the like, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed. In one transistor, channel widths in all regions do not necessarily have the same value. In other words, the channel width of one transistor is not fixed to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) is sometimes different from a channel width shown in a top view of a transistor (hereinafter also referred to as an “apparent channel width”). For example, in a transistor having a gate electrode covering side surfaces of a semiconductor layer, an effective channel width is greater than an apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a gate electrode covering a side surface of a semiconductor layer, the proportion of a channel formation region formed in the side surface of the semiconductor layer may be increased. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view.

In such a case, measuring an effective channel width is difficult in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, measuring an effective channel width accurately is difficult.

Thus, in this specification, an apparent channel width is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, the term “channel width” may denote a surrounded channel width, an apparent channel width, or an effective channel width. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.

A surrounded channel width may be used to calculate the field-effect mobility, the current value per channel width, and the like of a transistor. In this case, the obtained value is sometimes different from the value obtained by using an effective channel width for the calculation.

Note that impurities in a semiconductor refer to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, the density of states (DOS) in a semiconductor may be increased, the carrier mobility may be decreased, or the crystallinity may be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. In the case of an oxide semiconductor, water may function as an impurity. Furthermore, in the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities. In the case where the semiconductor is silicon, examples of an impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, the term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. In addition, the term “perpendicular” or “orthogonal” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. In addition, the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

In the specification and the like, the terms “identical”, “the same”, “equal”, “uniform”, and the like (including synonyms thereof) used in describing calculation values and actual measurement values allow for a margin of error of ±20% unless otherwise specified.

In this specification and the like, in the case where an etching step (removal step) is performed after a resist mask is formed by a photolithography method, the resist mask is removed after the etching step, unless otherwise specified.

In this specification and the like, a high power supply potential V_(DD) (hereinafter also simply referred to as V_(DD) or H potential) is a power supply potential higher than a low power supply potential V_(SS). The low power supply potential V_(SS) (hereinafter also simply referred to as V_(SS) or L potential) is a power supply potential lower than the high power supply potential V_(DD). In addition, a ground (GND) potential (also referred to as “GND”) can be used as V_(DD) or V_(SS). For example, in the case where a ground potential is used as V_(DD), V_(SS) is lower than the ground potential, and in the case where a ground potential is used as V_(SS), V_(DD) is higher than the ground potential.

Note that the terms “film” and “layer” can be used interchangeably depending on the case or the circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases.

Furthermore, unless otherwise specified, transistors described in this specification and the like are enhancement-type (normally-off-type) field effect transistors. Unless otherwise specified, a transistor described in this specification and the like refers to an n-channel transistor. Thus, unless otherwise specified, the threshold voltage (also referred to as “V_(th)”) is larger than 0 V.

Embodiment 1

Providing transistors having different electrical characteristics over the same layer can increase the degree of freedom in design of a semiconductor device and the integration degree in the semiconductor device. In this embodiment, an example of an embodiment where transistors having different electrical characteristics are provided over the same layer while an increase in the number of manufacturing steps is suppressed will be described.

<Structure Example of Semiconductor Device 1000>

FIG. 1A is a cross-sectional view of a semiconductor device 1000. The semiconductor device 1000 includes a transistor 100 and a transistor 200. The transistors 100 and 200 have different structures. FIG. 1A illustrates cross sections of the transistors 100 and 200 over the substrate 101. FIG. 1A corresponds to a cross-sectional view taken along dashed-dotted line L1-L2 in FIG. 2A and a cross-sectional view taken along dashed-dotted line L3-L4 in FIG. 3A.

FIG. 2A is a plan view of the transistor 100. FIG. 2B is a cross-sectional view taken along dashed-dotted line L1-L2 and a cross-sectional view taken along dashed-dotted line W1-W2 in FIG. 2A. In FIG. 2B, the cross-sectional view along L1-L2 is taken in the channel length direction of the transistor 100 and the cross-sectional view along W1-W2 is taken in the channel width direction of the transistor 100. FIG. 2C is an enlarged view of a portion 131 in FIG. 2B. FIG. 2D is an enlarged view of a portion 132 in FIG. 2B.

FIG. 3A is a plan view of the transistor 200. FIG. 3B is a cross-sectional view taken along dashed-dotted line L3-L4 and a cross-sectional view taken along dashed-dotted line W3-W4 in FIG. 3A. In FIG. 3B, the cross-sectional view along L3-L4 is taken in the channel length direction of the transistor 200 and the cross-sectional view along W3-W4 is taken in the channel width direction of the transistor 200. FIG. 3C is an enlarged view of a portion 133 in FIG. 3B.

FIGS. 1B and 1C each show a V_(g)-I_(d) curve, which is one of the electrical characteristics of a transistor. The horizontal axis of V_(g)-I_(d) curves shown in FIGS. 1B and 1C represents a potential difference (V_(g)) between a gate and a source regarded as a basis. The vertical axis represents current flowing to a drain (I_(d)) of the transistor on a logarithmic scale.

The transistors 100 and 200 are each a transistor including a back gate. FIG. 1B shows the V_(g)-I_(d) curve of the transistor 100 when the potential of the back gate is set to the same as that of the source or the gate. FIG. 1C shows the V_(g)-I_(d) curve of the transistor 200 when the potential of the back gate is set to the same as that of the source or the gate. As shown in FIGS. 1B and 1C, the transistors 100 and 200 have different transistor characteristics. The V_(g)-I_(d) curve of the transistor 200 is shifted in the positive direction compared with that in the V_(g)-I_(d) curve of the transistor 100. In other words, the transistor 200 has higher V_(th) than the transistor 100.

The transistors 100 and 200 are described with reference to drawings.

[Transistor 100]

The transistor 100 is a kind of top-gate transistor. The transistor 100 includes an electrode 105_1, an insulating layer 106, an insulating layer 107, an insulating layer 108, a semiconductor layer 109_1 a, a semiconductor layer 109_1 b, a semiconductor layer 109_1 c, an electrode 110_1 a, an electrode 110_1 b, a layer 128_1 a, a layer 128_1 b, a layer 129_1 a, a layer 129_1 b, an insulating layer 111_1, and an electrode 112_1 (see FIGS. 2A to 2C).

The transistor 100 illustrated in FIGS. 2A to 2C is provided over the substrate 101 with an insulating layer 102 and an insulating layer 103 located therebetween. Specifically, an insulating layer 104 is provided over the insulating layer 103, and a portion of the insulating layer 104 is removed and the electrode 105_1 is embedded. The insulating layer 106 is provided over the electrode 105_1 and the insulating layer 104, the insulating layer 107 is provided over the insulating layer 106, and the insulating layer 108 is provided over the insulating layer 107. The insulating layer 108 has a projection, the semiconductor layer 109_1 a is provided over the projection, and the semiconductor layer 109_1 b is provided over the semiconductor layer 109_1 a.

Furthermore, electrodes 110_1 a and 110_1 b are provided over the semiconductor layer 109_1 b. One of the electrode 110_1 a and the electrode 110_1 b can function as one of a source electrode and a drain electrode, and the other can function as the other of the source electrode and the drain electrode. Thus, a region of the semiconductor layer 109_1 b overlapping with the electrode 110_1 a can function as one of a source region and a drain region of the transistor 100. A region of the semiconductor layer 109_1 b overlapping with the electrode 110_1 b can function as the other of the source region and the drain region of the transistor 100. Thus, a region 121 a of the semiconductor layer 109_1 b that is sandwiched between the electrode 110_1 a and the electrode 110_1 b when seen in the plan view can function as a channel formation region.

Furthermore, the layer 128_1 a is provided over the electrode 110_1 a, and the layer 129_1 a is provided over the layer 128_1 a. A portion of a side surface of the electrode 110_1 a, a portion of a side surface of the layer 128_1 a, a portion of a side surface of the semiconductor layer 109_1 b, and a portion of a side surface of the semiconductor layer 109_1 a are covered with the layer 129_1 a.

Furthermore, the layer 128_1 b is provided over the electrode 110_1 b, and the layer 129_1 b is provided over the layer 128_1 b. A portion of a side surface of the electrode 110_1 b, a portion of a side surface of the layer 128_1 b, a portion of a side surface of the semiconductor layer 109_1 b, and a portion of a side surface of the semiconductor layer 109_1 a are covered with the layer 129_1 b.

An opening is formed in a region of an insulating layer 114 overlapping with the region 121 a, and the semiconductor layer 109_1 c is provided along the side and bottom surfaces of the opening. The semiconductor layer 109_1 c is in contact with the semiconductor layer 109_1 b at the bottom surface of the opening. In the opening, the insulating layer 111_1 is provided along the side and bottom surfaces of the opening with the semiconductor layer 109_1 c located between the insulating layer 111_1 and the side and bottom surfaces of the opening. In addition, the electrode 112_1 is provided in the opening with the semiconductor layer 109_1 c and the insulating layer 111_1 located between the electrode 112_1 and the side and bottom surfaces of the opening.

Note that the opening is wider than the semiconductor layer 109_1 a and the semiconductor layer 109_1 b in the cross section in the channel width direction. Thus, in the region 121 a, side surfaces of the semiconductor layers 109_1 a and 109_1 b are covered with the semiconductor layer 109_1 c.

An insulating layer 115 is provided over the insulating layer 114, and an electrode 117_1 a, an electrode 117_1 b, and an electrode 117_1 c are provided over the insulating layer 115. The electrode 117_1 a is electrically connected to the electrode 110_1 a through an electrode 116_1 a in an opening formed by removing portions of the insulating layers 115 and 114 and the layers 129_1 a and 128_1 a. The electrode 117_1 b is electrically connected to the electrode 110_1 b through an electrode 116_1 b in an opening formed by removing portions of the insulating layers 115 and 114 and the layers 129_1 b and 128_1 b. The electrode 117_1 c is electrically connected to the electrode 112_1 through an electrode 116_1 c in an opening formed by removing a portion of the insulating layer 115.

[S-Channel Structure]

As illustrated in FIG. 2B, in the transistor 100, the semiconductor layer 109_1 b is located between the electrode 105_1 and the electrode 112_1 in the channel width direction. As described above, the insulating layer 108 has the projection. The semiconductor layer 109_1 a and the semiconductor layer 109_1 b are provided over the projection. By providing the projection, a bottom surface of the electrode 112_1 in a region not overlapping with the projection (a region not overlapping with the semiconductor layer 109_1 b) can be closer to the substrate than a bottom surface of the semiconductor layer 109_1 b is. The height of the projection is preferably larger than or equal to the thickness of the insulating layer 111_1. Alternatively, the height of the projection is preferably greater than or equal to the sum of the thickness of the insulating layer 111_1 and the thickness of the semiconductor layer 109_1 c. Thus, the side surface of the semiconductor layer 109_1 b can be covered with the electrode 112_1.

In other words, the transistor 100 can have a structure in which the semiconductor layer 109_1 b can be electrically surrounded by an electric field between the electrode 105_1 and the electrode 112_1. Such a structure of a transistor in which a semiconductor layer where a channel is formed is electrically surrounded by an electric field between conductive layers (the electrodes 105_1 and 112_1 in the transistor 100) is called a surrounded channel (s-channel) structure. In the transistor 100 having an s-channel structure, a channel can be formed in the whole (bulk) of the semiconductor layer 109_1 b. In the s-channel structure, the drain current of the transistor can be increased, so that a larger amount of on-state current (current which flows between the source and the drain when the transistor is on) can be obtained. Furthermore, the entire channel formation region of the semiconductor layer 109_1 b can be depleted by the electric field between the electrode 105_1 and the electrode 112_1. Accordingly, the off-state current of the s-channel transistor can be further reduced. When the channel width is shortened, the effects of the s-channel structure, such as an increase in on-state current and a reduction in off-state current, can be enhanced.

[Gate Electrode and Back Gate Electrode]

One of the electrodes 105_1 and 112_1 can function as a gate electrode and the other can function as a back gate electrode. In general, a gate electrode and a back gate electrode are formed using a conductive layer and positioned so that the channel formation region of the semiconductor layer is located between the gate electrode and the back gate electrode. Thus, the back gate electrode can function in a manner similar to that of the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode or may be a ground potential or a predetermined potential. By changing the potential of the back gate electrode independently of the potential of the gate electrode, the threshold voltage of the transistor can be changed.

The electrode 105_1 and the electrode 112_1 can each function as a gate electrode. Thus, the insulating layers 106, 107, 108, and 111_1 can each function as a gate insulating layer.

In the case where one of the electrode 105_1 and the electrode 112_1 is referred to as a “gate electrode” or a “gate”, the other can be referred to as a “back gate electrode” or a “back gate”. For example, in the transistor 100, in the case where the electrode 105_1 is referred to as a “gate electrode”, the electrode 112_1 is referred to as a “back gate electrode”. In the case where the electrode 112_1 is used as a “gate electrode”, the transistor 100 can be regarded as a kind of bottom-gate transistor. Alternatively, one of the electrode 105_1 and the electrode 112_1 may be referred to as a “first gate electrode” or a “first gate”, and the other may be referred to as a “second gate electrode” or a “second gate”. Alternatively, one of the electrode 105_1 and the electrode 112_1 may be referred to as a “back gate”, and the other may be referred to as a “front gate”.

By providing the electrode 105_1 and the electrode 112_1 with the semiconductor layer 109_1 b provided therebetween and setting the potentials of the electrode 105_1 and the electrode 112_1 to be the same, a region of the semiconductor layer 109_1 b through which carriers flow is enlarged in the film thickness direction; thus, the number of transferred carriers is increased. As a result, the on-state current and the field-effect mobility of the transistor 100 are increased.

Therefore, the transistor 100 has large on-state current for its area. That is, the area occupied by the transistor 100 can be small for required on-state current. Therefore, a semiconductor device having a high degree of integration can be provided.

Furthermore, the gate electrode and the back gate electrode are formed using conductive layers and thus each have a function of preventing an electric field generated outside the transistor from influencing the semiconductor layer where the channel is formed (in particular, an electric field blocking function against static electricity and the like). When the back gate electrode is formed larger than the semiconductor layer to cover the semiconductor layer in the plan view, the electric field blocking function can be enhanced.

Since the electrode 105_1 and the electrode 112_1 each have a function of blocking an electric field from the outside, charges of charged particles and the like generated over the electrode 112_1 or under the electrode 105_1 do not influence the channel formation region in the semiconductor layer 109_1 b. Thus, degradation by a stress test (e.g., a negative gate bias temperature (−GBT) stress test in which negative charges are applied to a gate) can be reduced. In addition, the electrode 105_1 and the electrode 112_1 can block an electric field generated from the drain electrode so as not to affect the semiconductor layer. Thus, changes in the rising voltage of on-state current due to changes in drain voltage can be suppressed. Note that this effect is significant when a potential is applied to the electrodes 105_1 and 112_1.

The GBT stress test is one kind of acceleration test and can evaluate, in a short time, a change by long-term use (i.e., a change over time) in the characteristics of a transistor. In particular, the amount of change in the threshold voltage of the transistor between before and after the GBT stress test is an important indicator when the reliability of the transistor is examined. If the amount of change in the threshold voltage between before and after the GBT stress test is small, the transistor has higher reliability.

By providing the electrodes 105_1 and 112_1 and setting the potentials of the electrodes 105_1 and 112_1 to be the same, the amount of change in threshold voltage is reduced. Accordingly, variation in electrical characteristics among a plurality of transistors is also reduced.

The transistor including the back gate electrode has a smaller change in threshold voltage by a positive GBT stress test in which positive charges are applied to a gate than a transistor including no back gate electrode.

In the case where light is incident on the back gate electrode side, when the back gate electrode is formed using a light-blocking conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, photodegradation of the semiconductor layer can be prevented and deterioration in electrical characteristics of the transistor, such as a shift of the threshold voltage, can be prevented.

[Transistor 200]

The transistor 200 is a kind of top-gate transistor. The transistor 200 includes an electrode 105_2, the insulating layer 106, the insulating layer 107, the insulating layer 108, a semiconductor layer 109_2 a 1, a semiconductor layer 109_2 a 2, a semiconductor layer 109_2 b 1, a semiconductor layer 109_2 b 2, a semiconductor layer 109_2 c, an electrode 110_2 a, an electrode 110_2 b, a layer 128_2 a, a layer 128_2 b, a layer 129_2 a, a layer 129_2 b, an insulating layer 111_2, and an electrode 112_2 (see FIGS. 3A to 3C).

The transistor 200 illustrated in FIGS. 3A to 3C is provided over the substrate 101 with the insulating layer 102 and the insulating layer 103 located therebetween. Specifically, the insulating layer 104 is provided over the insulating layer 103, and a portion of the insulating layer 104 is removed and the electrode 105_2 is embedded. The insulating layer 106 is provided over the electrode 105_2 and the insulating layer 104, the insulating layer 107 is provided over the insulating layer 106, and the insulating layer 108 is provided over the insulating layer 107.

The insulating layer 108 includes a first projection and a second projection. The transistor 200 includes the semiconductor layer 109_2 a 1 over the first projection and the semiconductor layer 109_2 b 1 over the semiconductor layer 109_2 a 1. The transistor 200 includes the electrode 110_2 a over the semiconductor layer 109_2 b 1, the layer 128_2 a over the electrode 110_2 a, and the layer 129_2 a over the layer 128_2 a. The transistor 200 includes the semiconductor layer 109_2 a 2 over the second projection and the semiconductor layer 109_2 b 2 over the semiconductor layer 109_2 a 2. The transistor 200 includes the electrode 110_2 b over the semiconductor layer 109_2 b 2, the layer 128_2 b over the electrode 110_2 b, and the layer 129_2 b over the layer 128_2 b.

One of the electrode 110_2 a and the electrode 110_2 b can function as one of a source electrode and a drain electrode, and the other can function as the other of the source electrode and the drain electrode. Thus, one of the semiconductor layer 109_2 b 1 and the semiconductor layer 109_2 b 2 can function as one of a source region and a drain region of the transistor 200. The other of the semiconductor layer 109_2 b 1 and the semiconductor layer 109_2 b 2 can function as the other of the source region and the drain region of the transistor 200.

The layer 128_2 a is provided over the electrode 110_2 a, and the layer 129_2 a is provided over the layer 128_2 a. A portion of a side surface of the electrode 110_2 a, a portion of a side surface of the layer 128_2 a, a portion of a side surface of the semiconductor layer 109_2 b 1, and a portion of a side surface of the semiconductor layer 109_2 a 1 are covered with the layer 129_2 a.

The layer 128_2 b is provided over the electrode 110_2 b, and the layer 129_2 b is provided over the layer 128_2 b. A portion of a side surface of the electrode 110_2 b, a portion of a side surface of the layer 128_2 b, a portion of a side surface of the semiconductor layer 109_2 b 2, and a portion of a side surface of the semiconductor layer 109_2 a 2 are covered with the layer 129_2 b. A region 121 b of the semiconductor layer 109_2 c that is sandwiched between the semiconductor layer 109_2 b 1 and the semiconductor layer 109_2 b 2 when seen in the plan view can function as a channel formation region.

An opening is formed in a region of the insulating layer 114 overlapping with the region 121 b. The semiconductor layer 109_2 c is provided along the side and bottom surfaces of the opening. Portions of the semiconductor layers 109_2 b 1 and 109_2 b 2 are exposed in the opening. The semiconductor layer 109_2 c is in contact with the semiconductor layer 109_2 b 1 and the semiconductor layer 109_2 b 2 in the opening. In the opening, the insulating layer 111_2 is provided along the side and bottom surfaces of the opening with the semiconductor layer 109_2 c located therebetween. Furthermore, in the opening, the electrode 112_2 is provided with the semiconductor layer 109_2 c and the insulating layer 111_2 located therebetween.

The insulating layer 115 is provided over the insulating layer 114, and an electrode 117_2 a, an electrode 117_2 b, and an electrode 117_2 c are provided over the insulating layer 115. The electrode 117_2 a is electrically connected to the electrode 110_2 a through an electrode 116_2 a in an opening formed by removing portions of the insulating layers 115 and 114 and the layers 129_2 a and 128_2 a. The electrode 117_2 b is electrically connected to the electrode 110_2 b through an electrode 116_2 b in an opening formed by removing portions of the insulating layers 115 and 114 and the layers 129_2 b and 128_2 b. The electrode 117_2 c is electrically connected to the electrode 112_2 through an electrode 116_2 c in an opening formed by removing a portion of the insulating layer 115.

As in the transistor 100, one of the electrode 1052 and the electrode 112_2 in the transistor 200 can function as a gate electrode, and the other can function as a back gate electrode. Thus, the insulating layers 106, 107, 108, and 111_2 can each function as a gate insulating layer.

In the case where one of the electrode 105_2 and the electrode 112_2 is simply referred to as a “gate electrode” or a “gate”, the other can be referred to as a “back gate electrode” or a “back gate”. For example, in the transistor 200, in the case where the electrode 105_2 is referred to as a “gate electrode”, the electrode 112_2 is referred to as a “back gate electrode”. In the case where the electrode 112_2 is used as a “gate electrode”, the transistor 200 can be regarded as a kind of bottom-gate transistor. Alternatively, one of the electrode 105_2 and the electrode 112_2 may be referred to as a “first gate electrode” or a “first gate”, and the other may be referred to as a “second gate electrode” or a “second gate”. Alternatively, one of the electrode 105_2 and the electrode 112_2 may be referred to as a “back gate”, and the other may be referred to as a “front gate”.

In this specification and the like, the electrode 105_1 and the electrode 105_2 may be collectively referred to as an “electrode 105”. The semiconductor layer 109_1 a, the semiconductor layer 109_2 a 1, and the semiconductor layer 109_2 a 2 may be collectively referred to as a “semiconductor layer 109 a”. The semiconductor layer 109_2 a 1 and the semiconductor layer 109_2 a 2 may be collectively referred to as a “semiconductor layer 109_2 a”. The semiconductor layer 109_1 b, the semiconductor layer 109_2 b 1, and the semiconductor layer 109_2 b 2 may be collectively referred to as a “semiconductor layer 109 b”. The semiconductor layer 109_2 b 1 and the semiconductor layer 109_2 b 2 may be collectively referred to as a “semiconductor layer 109_2 b”. The semiconductor layer 109_1 c and the semiconductor layer 109_2 c may be collectively referred to as a “semiconductor layer 109 c”. The semiconductor layer 109 a, the semiconductor layer 109 b, and the semiconductor layer 109 c may be collectively referred to as a “semiconductor layer 109”. The layer 128_1 a, the layer 128_1 b, the layer 128_2 a, and the layer 128_2 b may be collectively referred to as a “layer 128”. The layer 128_1 a and the layer 128_1 b may be collectively referred to as a “layer 128_1”. The layer 128_2 a and the layer 128_2 b may be collectively referred to as a “layer 128_2”. The layer 129_1 a, the layer 129_1 b, the layer 129_2 a, and the layer 129_2 b may be collectively referred to as a “layer 129”. The layer 129_1 a and the layer 129_1 b may be collectively referred to as a “layer 129_1”. The layer 129_2 a and the layer 129_2 b may be collectively referred to as a “layer 129_2”. The insulating layer 111_1 and the insulating layer 111_2 may be collectively referred to as an “insulating layer 111”. The electrode 110_1 a, the electrode 110_1 b, the electrode 110_2 a, and the electrode 110_2 b may be collectively referred to as an “electrode 110”. The electrode 110_1 a and the electrode 110_1 b may be collectively referred to as an “electrode 110_1”. The electrode 110_2 a and the electrode 110_2 b may be collectively referred to as an “electrode 110_2”. The electrode 112_1 and the electrode 112_2 may be collectively referred to as an “electrode 112”. The insulating layer 113_1 and the insulating layer 113_2 may be collectively referred to as an “insulating layer 113”. The electrode 116_1 a, the electrode 116_1 b, the electrode 116_1 c, the electrode 116_2 a, the electrode 116_2 b, and the electrode 116_2 c may be collectively referred to as an “electrode 116”. The electrode 116_1 a, the electrode 1161 b, and the electrode 116_1 c may be collectively referred to as an “electrode 116_1”. The electrode 116_2 a, the electrode 116_2 b, and the electrode 116_2 c may be collectively referred to as an “electrode 116_2”. The electrode 117_1 a, the electrode 117_1 b, the electrode 117_1 c, the electrode 117_2 a, the electrode 117_2 b, and the electrode 117_2 c may be collectively referred to as an “electrode 117”. The electrode 117_1 a, the electrode 117_1 b, and the electrode 117_1 c may be collectively referred to as an “electrode 117_1”. The electrode 117_2 a, the electrode 117_2 b, and the electrode 117_2 c may be collectively referred to as an “electrode 117_2”.

In the transistor 100, a channel is formed in the semiconductor layer 109 b. In the transistor 200, a channel is formed in the semiconductor layer 109 c. The semiconductor layer 109 b and the semiconductor layer 109 c are preferably formed using semiconductor materials having different physical properties. When the semiconductor layer 109 b and the semiconductor layer 109 c are formed using semiconductor materials having different physical properties, the transistor 100 and the transistor 200 can have different electrical characteristics.

When semiconductor materials having different bandgaps are used for the semiconductor layers 109 b and 109 c, for example, the transistors 100 and 200 can have different field-effect mobilities. Specifically, when a semiconductor material having a larger bandgap than that of the semiconductor layer 109 b is used for the semiconductor layer 109 c, the field-effect mobility of the transistor 200 can be lower than that of the transistor 100. Similarly, the off-state current of the transistor 200 can be lower than that of the transistor 100.

When a semiconductor material having lower electron affinity than that of the semiconductor layer 109 b is used for the semiconductor layer 109 c, for example, the transistor 200 can have higher V_(th) than the transistor 100. Specifically, when the semiconductor layer 109 b is an In-M-Zn oxide (an oxide containing In, an element M, and Zn) at an atomic ratio of x₂:y₂:z₂ and the semiconductor layer 109 c is an In-M-Zn oxide at an atomic ratio of x₁:y₁:z₁, y₁/x₁ needs to be larger than y₂/x₂. With such In-M-Zn oxides, the transistor 200 can have larger V_(th) than the transistor 100.

When the semiconductor layer 109_2 b 1 is provided in contact with the electrode 110_2 a and the semiconductor layer 109_2 c, variation in electrical characteristics of the transistor 200 can be reduced. When the semiconductor layer 109_2 b 2 is provided in contact with the electrode 110_2 b and the semiconductor layer 109_2 c, variation in electrical characteristics of the transistor 200 can be reduced. The effects of the semiconductor layers 109_2 b 1 and 109_2 b 2 are described later in Example.

<Materials> [Substrate]

There is no particular limitation on a material used for the substrate 101 as long as the material has heat resistance high enough to withstand at least heat treatment performed later. For example, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like or a compound semiconductor substrate made of silicon germanium or the like can be used as the substrate 101. Alternatively, an SOI substrate, a semiconductor substrate on which a semiconductor element such as a strained transistor or a FIN-type transistor is provided, or the like can also be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like that can be used for a high-electron-mobility transistor (HEMT) may be used. The substrate 101 is not limited to a simple supporting substrate, and may be a substrate where a device such as a transistor is formed. In this case, at least one of the gate, the source, and the drain of the transistor 100 and/or the transistor 200 may be electrically connected to the device.

Still alternatively, as the substrate 101, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. Note that a flexible substrate may be used as the substrate 101. In the case where a flexible substrate is used, the transistor, a capacitor, or the like may be directly formed over the flexible substrate; or the transistor, the capacitor, or the like may be formed over a manufacturing substrate and then separated from the manufacturing substrate and transferred onto the flexible substrate. To separate and transfer the transistor, the capacitor, or the like from the manufacturing substrate to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor, the capacitor, or the like.

For the flexible substrate, for example, metal, an alloy, resin, glass, or fiber thereof can be used. The flexible substrate used as the substrate 101 preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate used as the substrate 101 is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10⁻³/K, lower than or equal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate because of its low coefficient of linear expansion.

[Insulating Layer]

The insulating layers 102 to 104, 106 to 108, 111, and 113 to 115 can be formed with a single layer or a stack of layers of one or more materials selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. Alternatively, a material in which two or more materials selected from an oxide material, a nitride material, an oxynitride material, and a nitride oxide material are mixed may be used.

Note that in this specification, a nitride oxide refers to a compound that includes more nitrogen than oxygen. An oxynitride refers to a compound that includes more oxygen than nitrogen. The content of each element can be measured by Rutherford backscattering spectrometry (RBS), for example.

It is particularly preferable that the insulating layer 115 and the insulating layer 102 and/or the insulating layer 103 be formed using an insulating material that is relatively impermeable to impurities. Examples of such an insulating material include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride. A single layer or a stack including any of these materials may be used.

When the insulating material that is relatively impermeable to impurities is used for the insulating layer 102 and/or the insulating layer 103, impurity diffusion from the substrate 101 side can be suppressed, and the reliability of the transistor can be improved. When the insulating material that is relatively impermeable to impurities is used for the insulating layer 115, impurity diffusion from layers above the insulating layer 115 can be suppressed, and the reliability of the transistor can be improved.

Note that a stack of a plurality of insulating layers formed with these materials may be used as the insulating layer 115 and the insulating layer 102 and/or the insulating layer 103. One of the insulating layer 102 and the insulating layer 103 may be omitted.

When an oxide semiconductor is used for the semiconductor layer 109, the hydrogen concentrations in the insulating layers are preferably lowered in order to prevent an increase in the hydrogen concentration in the semiconductor layer 109. Specifically, the hydrogen concentration in the insulating layer that is measured by secondary ion mass spectrometry (SIMS) is set lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³, more preferably lower than or equal to 1×10¹⁹ atoms/cm³, still more preferably lower than or equal to 5×10¹⁸ atoms/cm³. It is particularly preferable to lower the hydrogen concentrations of the insulating layers 104, 106 to 108, 111, and 114. It is preferable to lower at least the hydrogen concentrations of the insulating layers 108, 111, and 114 in contact with the semiconductor layer 109.

Furthermore, the nitrogen concentrations in the insulating layers are preferably low in order to prevent an increase in the nitrogen concentration in the semiconductor layer 109. Specifically, the nitrogen concentration in the insulating layer, which is measured by SIMS, is set lower than or equal to 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, more preferably lower than or equal to 1×10¹⁸ atoms/cm³, still more preferably lower than or equal to 5×10¹⁷ atoms/cm³.

It is preferable that a region of the insulating layer 108 which is in contact with at least the semiconductor layer 109 and a region of the insulating layer 111 which is in contact with at least the semiconductor layer 109 preferably have few defects and typically have as few signals observed by electron spin resonance (ESR) spectroscopy as possible. Examples of the signals include a signal due to an E′ center observed at a g-factor of 2.001. Note that the E′ center is due to the dangling bond of silicon. As the insulating layer 108 and the insulating layer 111, a silicon oxide layer or a silicon oxynitride layer whose spin density due to the E′ center is lower than or equal to 3×10¹⁷ spins/cm³, preferably lower than or equal to 5×10¹⁶ spins/cm³ can be used.

In addition to the above-described signal, a signal due to nitrogen dioxide (NO₂) might be observed. The signal is divided into three signals according to the N nuclear spin; a first signal, a second signal, and a third signal. The first signal is observed at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039. The second signal is observed at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003. The third signal is observed at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966.

It is suitable to use an insulating layer whose spin density of a signal due to nitrogen dioxide (NO₂) is higher than or equal to 1×10¹⁷ spins/cm³ and lower than 1×10¹⁸ spins/cm³ as the insulating layer 108 and the insulating layer 111, for example.

Note that nitrogen oxide (NO_(x)) such as nitrogen dioxide (NO₂) forms a state in the insulating layer. The state is positioned in the energy gap of the oxide semiconductor layer. Thus, when nitrogen oxide (NO_(x)) is diffused to the interface between the insulating layer and the oxide semiconductor layer, an electron can potentially be trapped by the state on the insulating layer side. As a result, the trapped electrons remain in the vicinity of the interface between the insulating layer and the oxide semiconductor layer; thus, the threshold voltage of the transistor is shifted in the positive direction. Therefore, a shift in the threshold voltage of the transistor can be reduced when a film with a low nitrogen oxide content is used as the insulating layer 108 and the insulating layer 111.

As an insulating layer that releases little nitrogen oxide (NO_(x)), for example, a silicon oxynitride layer can be used. The silicon oxynitride layer is a film of which the amount of released ammonia is larger than the amount of released nitrogen oxide (NO_(x)) in thermal desorption spectroscopy (TDS); the typical amount of released ammonia is greater than or equal to 1×10¹⁸/cm³ and less than or equal to 5×10¹⁹/cm³. Note that the released amount of ammonia is the total amount of ammonia released by heat treatment in a range from 50° C. to 650° C. or a range from 50° C. to 550° C. in TDS.

Since nitrogen oxide (NO_(x)) reacts with ammonia and oxygen in heat treatment, the use of an insulating layer that releases a large amount of ammonia reduces nitrogen oxide (NO_(x)).

At least one of the insulating layers 108, 111, and 114 is preferably formed using an insulating layer from which oxygen is released by heating. Specifically, it is preferable to use an insulating layer of which the amount of released oxygen converted into oxygen atoms is 1.0×10¹⁸ atoms/cm³ or more, 1.0×10¹⁹ atoms/cm³ or more, or 1.0×10²⁰ atoms/cm³ or more, in TDS analysis performed under such a condition that a surface of the layer is heated at a temperature higher than or equal to 100° C. and lower than or equal to 700° C., preferably higher than or equal to 100° C. and lower than or equal to 500° C. Note that oxygen released by heating is also referred to as excess oxygen.

The insulating layer containing excess oxygen can be formed by performing treatment for adding oxygen to an insulating layer. The treatment for adding oxygen can be performed by heat treatment under an oxygen atmosphere, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like. As a gas for adding oxygen, an oxygen gas of ¹⁶O₂, ¹⁸O₂, or the like, a nitrous oxide gas, an ozone gas, or the like can be used. In this specification, the treatment for adding oxygen is also referred to as “oxygen doping treatment”.

A heat-resistant organic material such as a polyimide, an acrylic-based resin, a benzocyclobutene-based resin, a polyamide, or an epoxy-based resin may be used to form the insulating layer 114. Other than the above organic materials, a low-dielectric constant material (low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like can be used. Note that the insulating layer 114 may be formed by stacking a plurality of insulating layers formed using any of these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may contain, as a substituent, an organic group (e.g., an alkyl group or an aryl group) or a fluoro group. The organic group may contain a fluoro group.

There is no particular limitation on the method for forming the insulating layer 114, and any of the following methods which depend on a material thereof can be used: a sputtering method; an SOG method; spin coating; dipping; spray coating; a droplet discharging method (e.g., an ink-jet method); a printing method (e.g., screen printing or offset printing); or the like. When the baking step of the insulating layer 114 also serves as heat treatment for another layer, the transistor can be manufactured efficiently.

Any of the above insulating layers may be used as the layer 128. In the case where the layer 128 is an insulating layer, an insulating layer which is less likely to release oxygen and/or which is less likely to absorb oxygen is preferably used.

Any of the above insulating layers may be used as the layer 129. In the case where the layer 129 is an insulating layer, an insulating layer which is less likely to release oxygen and/or which is less likely to absorb oxygen is preferably used.

[Electrode]

As a conductive material for forming the electrodes 105, 110, 112, 116, and 117, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and the like can be used. Alternatively, a semiconductor having a high electric conductivity typified by polycrystalline silicon including an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

A conductive material containing the above metal element and oxygen may be used. A conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon is added, or indium gallium zinc oxide containing nitrogen may be used.

A stack of a plurality of conductive layers formed with the above materials may be used. For example, a layered structure formed using a material containing the above metal element and a conductive material containing oxygen may be used. Alternatively, a layered structure formed using a material containing the above metal element and a conductive material containing nitrogen may be used. Still alternatively, a layered structure formed using a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

Note that in the case where an oxide semiconductor is used for the semiconductor layer and a layered structure formed using a combination of a material including any of the metal elements listed above and a conductive material including oxygen is used as the gate electrode, the conductive material including oxygen is preferably provided on the semiconductor layer side. By providing the conductive material including oxygen on the semiconductor layer side, oxygen released from the conductive material is likely to be supplied to the semiconductor layer.

The electrode 116 may be formed using, for example, a conductive material with high embeddability, such as tungsten or polysilicon. A conductive material with high embeddability and a barrier layer (a diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer may be used in combination. Note that the electrode 116 may be referred to as a contact plug.

In particular, the electrode 105 in contact with the insulating layers 103 and 104 is preferably formed using a conductive material that is relatively impermeable to impurities. Furthermore, the electrode 116 in contact with the insulating layers 114 and 115 is preferably formed using a conductive material that is relatively impermeable to impurities. As an example of the conductive material that is relatively impermeable to impurities, tantalum nitride can be given.

When the insulating layers 103 and 115 are formed using an insulating material that is relatively impermeable to impurities and the electrodes 105 and 116 are formed using a conductive material that is relatively impermeable to impurities, diffusion of impurities into the transistors 100 and 200 can be further suppressed. Thus, the reliabilities of the transistors 100 and 200 can be further increased.

Any of the above conductive materials may be used for the layer 128. In the case where the layer 128 is formed using a conductive material, a conductive material which is less likely to release oxygen and/or which is less likely to absorb oxygen is preferably used.

Any of the above conductive materials may be used for the layer 129. In the case where the layer 129 is formed using a conductive material, a conductive material which is less likely to release oxygen and/or which is less likely to absorb oxygen is preferably used.

[Semiconductor Layer]

For the semiconductor layer 109, a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As a semiconductor material, silicon, germanium, or the like can be used. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, a nitride semiconductor, or the like, an organic semiconductor, or the like may be used.

In the case of using an organic semiconductor for the semiconductor layer 109, a low molecular organic material having an aromatic ring, a π-electron conjugated conductive polymer, or the like can be used. For example, rubrene, tetracene, pentacene, perylenediimide, tetracyanoquinodimethane, polythiophene, polyacetylene, or polyparaphenylene vinylene can be used.

The semiconductor layers 109 a to 109 c may be formed using semiconductors having different crystal states or different semiconductor materials.

The band gap of an oxide semiconductor is greater than or equal to 2 eV; thus, when the oxide semiconductor is used for the semiconductor layer 109, a transistor with an extremely low off-state current can be provided. Specifically, the off-state current per micrometer in channel width at room temperature (typically 25° C.) and at a source—drain voltage of 3.5 V can be lower than 1×10⁻²⁰ A, lower than 1×10⁻²² A, or lower than 1×10⁻²⁴ A. That is, the on/off ratio of the transistor can be greater than or equal to 20 digits and less than or equal to 150 digits. A transistor using an oxide semiconductor in the semiconductor layer 109 has high withstand voltage between its source and drain. Thus, a transistor with high reliability can be provided. Furthermore, a transistor with high output voltage and high withstand voltage can be provided. Furthermore, a semiconductor device or the like with high reliability can be provided. Furthermore, a semiconductor device with high output voltage and high withstand voltage can be provided.

In this specification and the like, a transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed is also referred to as an “OS transistor”. In this specification and the like, a transistor in which silicon having crystallinity is used for a semiconductor layer where a channel is formed is also referred to as a “crystalline Si transistor”.

The crystalline Si transistor tends to obtain relatively high mobility as compared to the OS transistor. On the other hand, the crystalline Si transistor has difficulty in obtaining extremely low off-state current unlike the OS transistor. Thus, it is important that the semiconductor material used for the semiconductor layer be selected depending on the purpose and the usage. For example, depending on the purpose and the usage, the OS transistor and the crystalline Si transistor may be used in combination.

In the case where the semiconductor layer 109 is formed using an oxide semiconductor layer, the oxide semiconductor layer is preferably formed by a sputtering method. The oxide semiconductor layer is preferably formed by a sputtering method, in which case the oxide semiconductor layer can have high density. In the case where the oxide semiconductor layer is formed by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as a sputtering gas. In addition, increasing the purity of the sputtering gas is necessary. For example, an oxygen gas or a rare gas used as a sputtering gas is a gas that is highly purified to have a dew point of −60° C. or lower, preferably −100° C. or lower. By using the sputtering gas that is highly purified, entry of moisture or the like into the oxide semiconductor layer can be prevented as much as possible.

In the case where an oxide semiconductor layer is formed by a sputtering method, it is preferable that moisture in a deposition chamber in a sputtering apparatus be removed as much as possible. For example, with an adsorption vacuum evacuation pump such as cryopump, the deposition chamber is preferably evacuated to be a high vacuum state (to a degree of about 5×10⁻⁷ Pa to 1×10⁻⁴ Pa). In particular, the partial pressure of gas molecules corresponding to H₂O (gas molecules corresponding to m/z=18) in the deposition chamber in the standby mode of the sputtering apparatus is preferably lower than or equal to 1×10⁻⁴ Pa, more preferably lower than or equal to 5×10⁻⁵ Pa.

Any of the above semiconductor layers may be used as the layer 128. Any of the above semiconductor layers may be used as the layer 129.

In this embodiment, the case where an oxide semiconductor is used for the semiconductor layer 109 and the layers 128 and 129 will be described.

[Oxide Semiconductor]

An oxide semiconductor of the present invention will be described below. An oxide semiconductor preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition to these, aluminum, gallium, yttrium, tin, or the like is preferably contained. Furthermore, one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.

Here, the case where an oxide semiconductor contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that two or more of the above elements may be used in combination as the element M.

First, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor of the present invention will be described with reference to FIGS. 49A to 49C. Note that the proportion of oxygen atoms is not shown in FIGS. 49A to 49C. The terms of the atomic ratio of indium, the element M, and zinc contained in the oxide semiconductor are denoted by [In], [M], and [Zn], respectively.

In FIGS. 49A to 49C, broken lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):1 (where −1≦α≦1), a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):5.

Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β (where β≧0), a line where the atomic ratio [In]:[M]:[Zn] is 1:2:8, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β.

Furthermore, an oxide semiconductor with the atomic ratio of [In]:[M]:[Zn]=0:2:1 or a neighborhood thereof in FIGS. 49A to 49C tends to have a spinel crystal structure.

FIGS. 49A and 49B illustrate examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor in one embodiment of the present invention.

FIG. 50 illustrates an example of the crystal structure of InMZnO₄ whose atomic ratio [In]:[M]:[Zn] is 1:1:1. In FIG. 50, the crystal structure of InMZnO₄ observed from the direction parallel to a b-axis is illustrated. Note that a metal element in a layer that contains M, Zn, and oxygen (hereinafter, this layer is referred to as an “(M,Zn) layer”) in FIG. 50 represents the element M or zinc. In that case, the proportion of the element M is the same as the proportion of zinc. The element M and zinc can be replaced with each other, and their arrangement is random.

InMZnO₄ has a layered crystal structure (also referred to as a layered structure) and includes one layer that contains indium and oxygen (hereinafter referred to as an In layer) for every two (M,Zn) layers that contain the element M, zinc, and oxygen, as illustrated in FIG. 50.

Indium and the element M can be replaced with each other. Therefore, when the element Min the (M,Zn) layer is replaced by indium, the layer can also be referred to as an (In,M,Zn) layer. In that case, a layered structure that includes one In layer for every two (In,M,Zn) layers is obtained.

An oxide semiconductor whose atomic ratio [In]:[M]:[Zn] is 1:1:2 has a layered structure that includes one In layer for every three (M,Zn) layers. In other words, if [Zn] is larger than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide semiconductor is crystallized.

Note that in the case where the number of (M,Zn) layers with respect to one In layer is not an integer in the oxide semiconductor, the oxide semiconductor might have plural kinds of layered structures where the number of (M,Zn) layers with respect to one In layer is an integer. For example, in the case of [In]:[Zn]=1:1:1.5, the oxide semiconductor might have the following layered structures: a layered structure of one In layer for every two (M,Zn) layers and a layered structure of one In layer for every three (M,Zn) layers.

For example, in the case where the oxide semiconductor is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target, depending on the substrate temperature in deposition.

A plurality of phases (e.g., two phases or three phases) exist in the oxide semiconductor in some cases. For example, with an atomic ratio [In]:[M]:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide semiconductor, a grain boundary might be formed between different crystal structures.

In addition, the oxide semiconductor containing indium in a higher proportion can have high carrier mobility (electron mobility). Therefore, an oxide semiconductor having a high content of indium has higher carrier mobility than that of an oxide semiconductor having a low content of indium.

In contrast, when the indium content and the zinc content in an oxide semiconductor become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[Zn]=0:1:0 and the vicinity thereof (e.g., a region C in FIG. 49C), insulation performance becomes better.

Accordingly, an oxide semiconductor of one embodiment of the present invention preferably has an atomic ratio represented by a region A in FIG. 49A. With the atomic ratio, a layered structure with high carrier mobility and a few grain boundaries is easily obtained.

A region B in FIG. 49B represents an atomic ratio of [In]:[M]:[Zn]=4:2:3 to 4:2:4.1 and the vicinity thereof. The vicinity includes an atomic ratio of [In]:[M]:[Zn]=5:3:4. An oxide semiconductor having an atomic ratio represented by the region B is an excellent oxide semiconductor that has particularly high crystallinity and high carrier mobility.

Note that a condition where an oxide semiconductor has a layered structure is not uniquely determined by an atomic ratio. The atomic ratio affects difficulty in forming a layered structure. Even with the same atomic ratio, whether a layered structure is formed or not depends on a formation condition. Therefore, the illustrated regions each represent an atomic ratio with which an oxide semiconductor has a layered structure, and boundaries of the regions A to C are not clear.

Next, the case where the oxide semiconductor is used for a transistor will be described.

Note that when the oxide semiconductor is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.

An oxide semiconductor with low carrier density is preferably used for the transistor. For example, an oxide semiconductor whose carrier density is lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, more preferably lower than 1×10¹⁰/cm³, and higher than or equal to 1×10⁻⁹/cm³ is used.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources and thus can have a low carrier density. The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap states in some cases.

Charges trapped by the trap states in the oxide semiconductor take a long time to be released and may behave like fixed charges. Thus, a transistor whose channel is formed in an oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases.

To obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. In addition, to reduce the concentration of impurities in the oxide semiconductor, the concentration of impurities in a film that is adjacent to the oxide semiconductor is preferably reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

Here, the influence of impurities in the oxide semiconductor will be described.

When silicon or carbon, which is one of Group 14 elements, is contained in the oxide semiconductor, defect states are formed. Thus, the concentration of silicon or carbon in the oxide semiconductor and around an interface with the oxide semiconductor (measured by SIMS) is set lower than or equal to 2×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁷ atoms/cm³.

When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to be normally-on. Therefore, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor measured by SIMS is set lower than or equal to 1×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁶ atoms/cm³.

When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor including, as a semiconductor, an oxide semiconductor that contains nitrogen is likely to be normally-on. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible; the nitrogen concentration measured by SIMS is set, for example, lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, more preferably lower than or equal to 1×10¹⁸ atoms/cm³, still more preferably lower than or equal to 5×10¹⁷ atoms/cm³.

Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor that contains hydrogen is likely to be normally-on. Accordingly, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration measured by SIMS is set lower than 1×10²⁰ atoms/cm³, preferably lower than 1×10¹⁹ atoms/cm³, more preferably lower than 5×10¹⁸ atoms/cm³, still more preferably lower than 1×10¹⁸ atoms/cm³.

When an oxide semiconductor with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.

For the semiconductor layer 109 b, an oxide semiconductor with a wide energy gap is used, for example. The energy gap of the semiconductor layer 109 b is, for example, greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, more preferably greater than or equal to 3 eV and less than or equal to 3.5 eV.

For example, in the case where an InGaZnOx_(X) (X>0) film is formed by a thermal CVD method as the semiconductor layer 109, trimethylindium (In(CH₃)₃), trimethylgallium (Ga(CH₃)₃), and dimethylzinc (Zn(CH₃)₂) are used. Without limitation to the above combination, triethylgallium (Ga(C₂H₅)₃) can be used instead of trimethylgallium, and diethylzinc (Zn(C₂H₅)₂) can be used instead of dimethylzinc.

For example, in the case where an InGaZnO_(X) (X>0) film is formed as the semiconductor layer 109 by the ALD method, an In(CH₃)₃ gas and an O₃ gas are sequentially introduced a plurality of times to form an InO₂ layer, a Ga(CH₃)₃ gas and an O₃ gas are sequentially introduced a plurality of times to form a GaO layer, and then a Zn(CH₃)₂ gas and an O₃ gas are sequentially introduced a plurality of times to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an InGaO₂ layer, an InZnO₂ layer, a GaInP layer, a ZnInO layer, or a GaZnO layer may be formed using these gases. Note that although an H₂O gas which is obtained by bubbling water with an inert gas such as Ar may be used instead of an O₃ gas, it is preferable to use an O₃ gas, which does not contain H. Instead of an In(CH₃)₃ gas, an In(C₂H₅)₃ gas or tris(acetylacetonato)indium may be used. Note that tris(acetylacetonato)indium is also referred to as In(acac)₃. Instead of a Ga(CH₃)₃ gas, a Ga(C₂H₅)₃ gas or tris(acetylacetonato)gallium may be used. Note that tris(acetylacetonato)gallium is also referred to as Ga(acac)₃. Furthermore, a Zn(CH₃)₂ gas or zinc acetate may be used. However, the deposition gas is not limited to these.

In the case where the semiconductor layer 109 is formed by a sputtering method, a target containing indium is preferably used in order to reduce the number of particles. In addition, if an oxide target having a high atomic ratio of the element M is used, the conductivity of the target may be decreased. Particularly in the case where a target containing indium is used, the conductivity of the target can be increased and DC discharge or AC discharge is facilitated; thus, deposition over a large substrate can be easily performed. Thus, semiconductor devices can be manufactured with improved productivity.

In the case where the semiconductor layer 109 is formed by a sputtering method, the atomic ratio of In to M and Zn contained in the target may be 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1:1:2, 1:4:4, 4:2:4.1, 1:3:2, or 1:3:4, for example.

In the cases where the semiconductor layer 109 is formed by a sputtering method, a film having an atomic ratio different from the atomic ratio of the target may be formed. Especially for zinc, the proportion of zinc atoms of a formed film is smaller than that of zinc atoms of the target in some cases. Specifically, the proportion of zinc atoms of the film may be approximately 40% to 90% of the proportion of zinc atoms of the target.

The semiconductor layer 109 a and the semiconductor layer 109 c are preferably formed using a material including one or more kinds of metal elements, other than oxygen, included in the semiconductor layer 109 b. With the use of such a material, interface states at interfaces between the semiconductor layer 109 a and the semiconductor layer 109 b and between the semiconductor layer 109 c and the semiconductor layer 109 b are less likely to be generated. Accordingly, carriers are not likely to be scattered or captured at the interfaces, which results in an improvement in field-effect mobility of the transistor. Furthermore, variation in threshold voltage (hereinafter also referred to as “V_(th)”) of the transistor can be reduced. Thus, a semiconductor device having favorable electrical characteristics can be obtained.

When the semiconductor layer 109 b is an In-M-Zn oxide containing In, the element M, and Zn at an atomic ratio of x₂:y₂:z₂ and each of the semiconductor layer 109 a and the semiconductor layer 109 c is an In-M-Zn oxide containing In, M, and Zn at an atomic ratio of x₁:y₁:z₁, y₁/x₁ is preferably larger than y₂/x₂. More preferably, the semiconductor layer 109 a, the semiconductor layer 109 c, and the semiconductor layer 109 b in which y₁/x₁ is 1.5 or more times as large as y₂/x₂ are selected. Still more preferably, the semiconductor layer 109 a, the semiconductor layer 109 c, and the semiconductor layer 109 b in which y₁/x₁ is 2 or more times as large as y₂/x₂ are selected. Still more preferably, the semiconductor layer 109 a, the semiconductor layer 109 c, and the semiconductor layer 109 b in which y₁/x₁ is 3 or more times as large as y₂/x₂ are selected. In the semiconductor layer 109 b of this case, y₁ is preferably larger than or equal to x₁ because the transistor can have stable electrical characteristics. However, when y₁ is five or more times as large as x₁, the field-effect mobility of the transistor is reduced; accordingly, y₁ is preferably smaller than five times x₁. When the oxide semiconductor layers 109 a and 109 c each have the above structure, each of the oxide semiconductor layers 109 a and 109 c can be a layer in which oxygen vacancy is less likely to occur than in the semiconductor layer 109 b.

In the case of using an In-M-Zn oxide as the semiconductor layer 109 a, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, more preferably less than 25 atomic % and greater than 75 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor layer 109 b, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and Mare preferably set to be greater than 25 atomic % and less than 75 atomic %, respectively, more preferably greater than 34 atomic % and less than 66 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor layer 109 c, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and Mare preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, more preferably less than 25 atomic % and greater than 75 atomic %, respectively. Note that the semiconductor layer 109 c and the semiconductor layer 109 a may be formed using the same type of oxide.

For example, an In—Ga—Zn oxide which is formed using a target having an atomic ratio of In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 or an In—Ga oxide which is formed using a target having an atomic ratio of In:Ga=1:9 or 7:93 can be used for each of the oxide semiconductor layers 109 a and 109 c containing In or Ga. Furthermore, an In—Ga—Zn oxide which is formed using a target having an atomic ratio of In:Ga:Zn=1:1:1 or 3:1:2 can be used for the semiconductor layer 109 b. Note that the atomic ratio of each of the oxide semiconductor layers 109 a, 109 b, and 109 c may vary within a margin of ±20% of the corresponding atomic ratio.

For the semiconductor layer 109 b, an oxide having an electron affinity higher than that of each of the semiconductor layer 109 a and the semiconductor layer 109 c is used. For example, for the semiconductor layer 109 b, an oxide having an electron affinity higher than that of each of the semiconductor layer 109 a and the semiconductor layer 109 c by 0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, more preferably 0.15 eV or higher and 0.4 eV or lower is used. Note that the electron affinity refers to an energy difference between the vacuum level and the conduction band minimum.

An indium gallium oxide has a small electron affinity and a high oxygen-blocking property. Therefore, the semiconductor layer 109 c preferably includes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, more preferably higher than or equal to 90%.

Note that the semiconductor layer 109 a and/or the semiconductor layer 109 c may be gallium oxide. For example, when gallium oxide is used for the semiconductor layer 109 c, a leakage current generated between the electrode 105 and the semiconductor layer 109 can be reduced. In other words, the off-state current of the transistor 100 can be reduced.

At this time, when a gate voltage is applied, a channel is formed in the semiconductor layer 109 b having the highest electron affinity among the oxide semiconductor layers 109 a to 109 c.

In order to give stable electrical characteristics to the OS transistor, it is preferable that impurities and oxygen vacancies in the oxide semiconductor layer be reduced to highly purify the oxide semiconductor layer so that at least the semiconductor layer 109 b can be regarded as an intrinsic or substantially intrinsic oxide semiconductor layer. Furthermore, it is preferable that at least the channel formation region of the semiconductor layer 109 b be regarded as an intrinsic or substantially intrinsic semiconductor layer.

The layer 129 (the layer 129 a and the layer 129 b) may be formed using a material and a method which are similar to those of the semiconductor layer 109. In the case where the layer 129 is formed using an oxide semiconductor layer, an oxide semiconductor layer which is less likely to release oxygen and/or which is less likely to absorb oxygen is preferably used.

[Energy Band Structure of Oxide Semiconductor Layer]

A function and an effect of the semiconductor layer 109 consisting of the oxide semiconductor layers 109_1 a, 109_1 b, and 109_1 c will be described using an energy band structure diagrams of FIGS. 4A and 4B. FIG. 4A illustrates the energy band structure of a portion along dashed-dotted line A1-A2 in FIGS. 2B and 2C. In other words, FIG. 4A illustrates the energy band structure of a channel formation region of the transistor 100.

In FIG. 4A, Ec382, Ec383 a, Ec383 b, Ec383 c, and Ec386 indicate the energy of the conduction band minimum of the insulating layer 108, the semiconductor layer 109_1 a, the semiconductor layer 109_1 b, the semiconductor layer 109_1 c, and the insulating layer 111_1, respectively.

Here, an electron affinity corresponds to a value obtained by subtracting an energy gap from a difference in energy between the vacuum level and the valence band maximum (the difference is also referred to as “ionization potential”). The energy gap can be measured using a spectroscopic ellipsometer (UT-300 manufactured by HORIBA Jobin Yvon SAS). The energy difference between the vacuum level and the valence band maximum can be measured using an ultraviolet photoelectron spectroscopy (UPS) device (VersaProbe manufactured by ULVAC-PHI, Inc.)

An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:3:2 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.5 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:3:4 has an energy gap of approximately 3.4 eV and an electron affinity of approximately 4.5 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:3:6 has an energy gap of approximately 3.3 eV and an electron affinity of approximately 4.5 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:6:2 has an energy gap of approximately 3.9 eV and an electron affinity of approximately 4.3 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:6:8 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.4 eV. An In—Ga—Zn oxide which is formed using a target having an atomic ratio of In:Ga:Zn=1:6:10 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.5 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:1:1 has an energy gap of approximately 3.2 eV and an electron affinity of approximately 4.7 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=3:1:2 has an energy gap of approximately 2.8 eV and an electron affinity of approximately 5.0 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=3:1:4 has an energy gap of approximately 2.8 eV and an electron affinity of approximately 4.6 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=4:2:4.1 has an energy gap of approximately 3.0 eV and an electron affinity of approximately 4.4 eV.

Since the insulating layer 108 and the insulating layer 111_1 are insulators, Ec382 and Ec386 are closer to the vacuum level than Ec383 a, Ec383 b, and Ec383 c (i.e., the insulating layer 108 and the insulating layer 111_1 have a smaller electron affinity than the semiconductor layer 109_1 a, the semiconductor layer 109_1 b, and the semiconductor layer 109_1 c).

Ec383 a is closer to the vacuum level than Ec383 b. Specifically, Ec383 a is preferably located closer to the vacuum level than Ec383 b by greater than or equal to 0.07 eV and less than or equal to 1.3 eV, more preferably greater than or equal to 0.1 eV and less than or equal to 0.7 eV, more preferably greater than or equal to 0.15 eV and less than or equal to 0.4 eV.

Ec383 c is closer to the vacuum level than Ec383 b. Specifically, Ec383 c is preferably located closer to the vacuum level than Ec383 b by greater than or equal to 0.07 eV and less than or equal to 1.3 eV, more preferably greater than or equal to 0.1 eV and less than or equal to 0.7 eV, more preferably greater than or equal to 0.15 eV and less than or equal to 0.4 eV.

Here, a mixed region of the semiconductor layer 109_1 a and the semiconductor layer 109_1 b might exist between the semiconductor layer 109_1 a and the semiconductor layer 109_1 b. A mixed region of the semiconductor layer 109_1 b and the semiconductor layer 109_1 c might exist between the semiconductor layer 109_1 b and the semiconductor layer 109_1 c. The mixed region has a low density of interface states. For that reason, the stack including the oxide semiconductor layers 109_1 a, 109_1 b, and 109_1 c has a band structure where energy at each interface and in the vicinity of the interface is changed continuously (continuous junction).

At this time, electrons move mainly in the semiconductor layer 109_1 b, not in the semiconductor layer 109_1 a and the semiconductor layer 109_1 c. Thus, when the interface state density at the interface between the semiconductor layer 109_1 a and the semiconductor layer 109_1 b and the interface state density at the interface between the semiconductor layer 109_1 b and the semiconductor layer 109_1 c are decreased, electron movement in the semiconductor layer 109_1 b is less likely to be inhibited and the on-state current of the transistor 100 can be increased.

Although trap states 390 due to impurities or defects might be formed at or near the interface between the semiconductor layer 109_1 a and the insulating layer 108 and at or near the interface between the semiconductor layer 109_1 c and the insulating layer 111_1, the semiconductor layer 109_1 b can be separated from the trap states owing to the existence of the semiconductor layer 109_1 a and the semiconductor layer 109_1 c.

In the case where the transistor 100 has an s-channel structure, a channel is formed in the whole of the semiconductor layer 109_1 b. Therefore, as the semiconductor layer 109_1 b has a larger thickness, a channel formation region becomes larger. In other words, the thicker the semiconductor layer 109_1 b is, the larger the on-state current of the transistor 100 is. The thickness of the semiconductor layer 109_1 b is 5 nm or larger, preferably 10 nm or larger, more preferably 20 nm or larger, still more preferably 50 nm or larger.

Moreover, the thickness of the semiconductor layer 109_1 c is preferably as small as possible to increase the on-state current of the transistor 100. The thickness of the semiconductor layer 109_1 c is less than 20 nm, preferably less than or equal to 10 nm, more preferably less than or equal to 5 nm. Meanwhile, the semiconductor layer 109_1 c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor layer 109_1 b where a channel is formed. For this reason, it is preferable that the semiconductor layer 109_1 c have a certain thickness. The semiconductor layer 109_1 c has a thickness of greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm, more preferably greater than or equal to 2 nm.

To improve reliability, preferably, the thickness of the semiconductor layer 109_1 a is large. The semiconductor layer 109_1 a has a thickness of greater than or equal to 10 nm, preferably greater than or equal to 20 nm, more preferably greater than or equal to 40 nm, still more preferably greater than or equal to 60 nm. When the thickness of the semiconductor layer 109_1 a is made large, the distance from an interface between the adjacent insulator (the insulating layer 108) and the semiconductor layer 109_1 a to the semiconductor layer 109_1 b, in which a channel is formed, can be large. However, to prevent the productivity of the transistor 100 or the semiconductor device including the transistor 100 from being decreased, the semiconductor layer 109_1 a has a thickness of, for example, less than or equal to 50 nm, preferably less than or equal to 20 nm, more preferably less than or equal to 10 nm.

The semiconductor layer 109_1 a may have a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor layer 109_1 b, where a channel is formed. The semiconductor layer 109_1 a may have an oxygen-blocking property to suppress outward diffusion of oxygen included in the semiconductor layer 109_1 b.

In the case where an electrode functioning as a gate electrode or a back gate electrode is provided below the semiconductor layer 109_1 a, the thickness of the semiconductor layer 109_1 a is preferably as small as possible to increase the on-state current of the transistor 100. In that case, the semiconductor layer 109_1 a includes a region with a thickness of less than 20 nm, preferably less than or equal to 10 nm, more preferably less than or equal to 5 nm, for example.

FIG. 4B illustrates the energy band structure of a portion along dashed-dotted line B1-B2 in FIG. 2D. In other words, FIG. 4B illustrates the energy band structure of a side surface of the semiconductor layer 109_1 b.

In FIG. 4B, Ec387, Ec384, and Ec383 b indicate the energy of the conduction band minimum of the insulating layer 114, that of the layer 129_1 b, and that of the semiconductor layer 109_1 b, respectively. Although the trap states 390 due to impurities or defects might be formed in the vicinity of the interface between the side surface of the semiconductor layer 109_1 b and the insulating layer 114, the side surface of the semiconductor layer 109_1 b can be apart from the trap states owing to the existence of the layer 129_1 b.

By providing the layer 129_1 b in contact with the side surface of the semiconductor layer 109_1 b, diffusion of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor layer 109_1 b through the side surface thereof can be prevented. Furthermore, outward diffusion of oxygen included in the semiconductor layer 109_1 b can be suppressed.

FIG. 5 illustrates the energy band structure of a portion along a dashed-dotted line C1-C2 in FIG. 3C. In other words, FIG. 5 illustrates the energy band structure of a channel formation region of the transistor 200.

In FIG. 5, Ec382, Ec383 c, and Ec386 indicate the energy of the conduction band minimum of the insulating layer 108, that of the semiconductor layer 109_2 c, and that of the insulating layer 111_2, respectively. Since a region of the semiconductor layer 109_2 c where a channel is formed is in direct contact with the insulating layer 108 and the insulating layer 111_2 in the transistor 200, the transistor 200 is likely to be affected by interface scattering and the trap states 390. Thus, the transistor 200 has lower on-state current, off-state current, and field-effect mobility than the transistor 100. Furthermore, the transistor 200 has higher V_(th) than the transistor 100.

Although the semiconductor layer of the transistor 100 has the above three-layer structure in this embodiment, one embodiment of the present invention is not limited thereto. For example, the semiconductor layer may have a two-layer structure without one of the semiconductor layer 109_1 a and the semiconductor layer 109_1 c. Alternatively, a single layer structure using any one of the semiconductor layer 109_1 a, the semiconductor layer 109_1 b, and the semiconductor layer 109_1 c may be employed. Alternatively, a four-layer structure in which any one of the above-described semiconductors is provided over or under the semiconductor layer 109_1 a or over or under the semiconductor layer 109_1 c may be employed. Still alternatively, it is possible to employ an n-layer structure (n is an integer of 5 or more) in which any one of the semiconductors described as examples of the semiconductor layer 109 a, the semiconductor layer 109 b, and the semiconductor layer 109 c is provided at two of the following positions: over the semiconductor layer 109 a; under the semiconductor layer 109 a; over the semiconductor layer 109 c; and under the semiconductor layer 109 c.

[Concentration of Impurities in Oxide Semiconductor Layer]

Note that silicon contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. Therefore, the silicon concentration of the semiconductor layer 109_1 b is preferably as low as possible. For example, a region with a silicon concentration of lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, more preferably lower than 2×10¹⁸ atoms/cm³ which is measured by SIMS is provided between the semiconductor layer 109_1 b and the semiconductor layer 109_1 a. A region with a silicon concentration of lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, more preferably lower than 2×10¹⁸ atoms/cm³ which is measured by SIMS is provided between the semiconductor layer 109_1 b and the semiconductor layer 109_1 c.

It is preferable to reduce the concentration of hydrogen in the semiconductor layer 109_1 a and the semiconductor layer 109_1 c in order to reduce the concentration of hydrogen in the semiconductor layer 109_1 b. The semiconductor layer 109_1 a and the semiconductor layer 109_1 c each have a region in which the concentration of hydrogen measured by SIMS is lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³, more preferably lower than or equal to 1×10¹⁹ atoms/cm³, still more preferably lower than or equal to 5×10¹⁸ atoms/cm³.

It is preferable to reduce the concentration of nitrogen in the semiconductor layer 109_1 a and the semiconductor layer 109_1 c in order to reduce the concentration of nitrogen in the semiconductor layer 109_1 b. The semiconductor layer 109_1 a and the semiconductor layer 109_1 c each have a region in which the concentration of nitrogen measured by SIMS is lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, more preferably lower than or equal to 1×10¹⁸ atoms/cm³, still more preferably lower than or equal to 5×10¹⁷ atoms/cm³.

Note that when copper enters the oxide semiconductor, an electron trap might be generated. The electron trap might shift the threshold voltage of the transistor in the positive direction. Therefore, the copper concentration at the surface of or in the semiconductor layer 109 b is preferably as low as possible. For example, the semiconductor layer 109 b preferably has a region in which the copper concentration is lower than or equal to 1×10¹⁹ atoms/cm³, lower than or equal to 5×10¹⁸ atoms/cm³, or lower than or equal to 1×10¹⁸ atoms/cm³.

[Deposition Method]

An insulating material for forming the insulating layers, a conductive material for forming the electrodes, or a semiconductor material for forming the semiconductor layers can be formed by a sputtering method, a spin coating method, a chemical vapor deposition (CVD) method (including a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method, a plasma enhanced CVD (PECVD) method, a high density plasma CVD method, a low pressure CVD (LPCVD) method, an atmospheric pressure CVD (APCVD) method, and the like), an atomic layer deposition (ALD) method, a molecular beam epitaxy (MBE) method, or a pulsed laser deposition (PLD) method.

By using a PECVD method, a high-quality film can be formed at a relatively low temperature. By using a deposition method that does not use plasma for deposition, such as an MOCVD method, an ALD method, or a thermal CVD method, a film can be formed with few defects because damage is not easily caused on a surface on which the film is deposited.

In the case where a film is formed by an ALD method, a gas that does not contain chlorine is preferably used as a material gas.

<Example of Method for Manufacturing Semiconductor Device 1000>

An example of a method for manufacturing the semiconductor device 1000 will be described with reference to FIGS. 6A to 6E, FIGS. 7A to 7D, FIGS. 8A to 8D, FIGS. 9A to 9C, FIGS. 10A to 10C, and FIGS. 11A to 11C. An L1-L2 cross section in each of FIGS. 6A to 11C corresponds to the cross section taken along dashed-dotted line L1-L2 in FIG. 2A. An L3-L4 cross section in each of FIGS. 6A to 11C corresponds to the cross section taken along dashed-dotted line L3-L4 in FIG. 3A.

[Step 1]

First, the insulating layer 102, the insulating layer 103, and the insulating layer 104 are sequentially formed over the substrate 101 (see FIG. 6A). In this embodiment, a single crystal silicon substrate (a p-type semiconductor substrate or an n-type semiconductor substrate) is used as the substrate 101.

In this embodiment, a silicon nitride film is deposited by a CVD method as the insulating layer 102. In this embodiment, an aluminum oxide film is deposited by an ALD method as the insulating layer 103. A dense insulating layer including reduced defects such as cracks or pinholes or having a uniform thickness can be formed by an ALD method. In this embodiment, a silicon oxide film is deposited by a CVD method as the insulating layer 104.

[Step 2]

Next, a resist mask is formed over the sample surface (not illustrated). The resist mask can be formed by a photolithography method, a printing method, an inkjet method, or the like as appropriate. Formation of the resist mask by a printing method, an inkjet method, or the like needs no photomask; thus, manufacturing cost can be reduced.

The formation of the resist mask by a photolithography method can be performed in such a manner that a photosensitive resist is irradiated with light through a photomask and a portion of the resist which has been exposed to light (or has not been exposed to light) is removed using a developing solution. Examples of light with which the photosensitive resist is irradiated include KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV) light, and the like. Alternatively, a liquid immersion technique may be employed in which light exposure is performed with a portion between a substrate and a projection lens filled with liquid (e.g., water). An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a photomask is not necessary in the case of using an electron beam or an ion beam. Note that a dry etching method such as ashing or a wet etching method using a dedicated stripper or the like can be used for removal of the resist mask. Both the dry etching method and the wet etching method may be used.

With the use of the resist mask as a mask, a portion of the insulating layer 104 is selectively removed to form an opening 181_1 and an opening 181_2 (see FIG. 6B). After that, the resist mask is removed. When the openings are formed, a portion of the insulating layer 103 is also removed in some cases. The insulating layer 104 can be removed by a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used.

[Step 3]

Next, a conductive layer 182 is formed over the Insulating layers 103 and 104 (see FIG. 6C). In this embodiment, a tungsten film is deposited by a sputtering method as the conductive layer 182.

[Step 4]

Next, chemical mechanical polishing (CMP) treatment (hereinafter also referred to as “CMP treatment”) is performed (see FIG. 6D). By CMP treatment, a portion of the conductive layer 182 is removed to form the electrode 105_1 and the electrode 105_2. At this time, a portion of a surface of the insulating layer 104 is also removed in some cases. By the CMP treatment, roughness of the sample surface can be reduced, and coverage with an insulating layer or a conductive layer to be formed later can be increased.

[Step 5]

Next, the insulating layer 106, the insulating layer 107, and the insulating layer 108 are sequentially formed (see FIG. 6E). In this embodiment, as each of the insulating layers 106 and 108, a 5-nm-thick silicon oxynitride film is deposited by a CVD method. The insulating layer 107 is preferably formed using a high-k material such as hafnium oxide, aluminum oxide, tantalum oxide, or yttrium oxide. When the insulating layer 107 is formed using any of these materials, the insulating layer 107 can function as a charge trap layer. The threshold voltage of the transistor 100 can be changed by injecting electrons into the insulating layer 107. For example, the injection of electrons into the insulating layer 107 can be performed with the use of the tunnel effect. By applying a positive voltage to the electrode 105, tunnel electrons can be injected into the insulating layer 107. In this embodiment, a 5-nm-thick aluminum oxide film is deposited as the insulating layer 107 by an ALD method.

As described above, the insulating layer 108 is preferably an insulating layer containing excess oxygen. Oxygen doping treatment may be performed after the formation of the insulating layer 108.

At least one of the insulating layers 106 and 107 is not necessarily formed.

[Step 6]

Next, the semiconductor layer 184 a, the semiconductor layer 184 b, the conductive layer 185, and the layer 186 are sequentially formed (see FIG. 7A). In this embodiment, the semiconductor layer 184 a is formed by a sputtering method using a target having a composition of In:Ga:Zn=1:3:2. An oxygen gas or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the amount of excess oxygen in the semiconductor layer 184 a can be increased. The proportion of oxygen in the sputtering gas is preferably 70% or more, more preferably 80% or more, still more preferably 100%. When a semiconductor layer containing excess oxygen is used as the semiconductor layer 184 a, oxygen can be supplied to the semiconductor layer 184 b by later heat treatment.

At the formation of the semiconductor layer 184 a, part of oxygen contained in the sputtering gas is supplied to the insulating layer 108 in some cases. As the amount of oxygen contained in the sputtering gas increases, the amount of oxygen supplied to the insulating layer 108 tends to increase. Part of oxygen supplied to the insulating layer 108 reacts with hydrogen left in the insulating layer 108 to produce water and the water is released from the insulating layer 108 by later heat treatment. Thus, the hydrogen concentration in the insulating layer 108 can be reduced.

The semiconductor layer 184 b is formed by a sputtering method using a target having a composition of In:Ga:Zn=4:2:4.1. At this time, when the proportion of oxygen in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient oxide semiconductor layer is formed. A transistor including an oxygen-deficient oxide semiconductor layer can have relatively high field-effect mobility.

In the case where an oxygen-deficient oxide semiconductor layer is used as the semiconductor layer 184 b, a semiconductor layer containing excess oxygen is preferably used as the semiconductor layer 184 a.

The semiconductor layer 184 b may be formed by a sputtering method using a target having a composition of In:Ga:Zn=1:1:1. The use of such an oxide semiconductor layer makes it possible to provide a highly reliable transistor.

In this embodiment, the layer 186 is formed by a sputtering method using a target having a composition of In:Ga:Zn=1:3:2. As the conductive layer 185, a tantalum nitride film is deposited by a sputtering method.

By introducing impurity elements into the semiconductor layer 184 b after the semiconductor layer 184 b is formed, the threshold voltage of the transistor 100 can be changed. Impurity elements can be introduced by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment using a gas containing impurity elements, or the like. In the case where impurity elements are introduced by an ion implantation method or the like, the introduction may be performed after the conductive layer 185 is formed or after the layer 186 is formed.

After the semiconductor layer 184 b is formed, oxygen doping treatment may be performed.

[Step 7]

Next, a resist mask is formed over the layer 186 by a photolithography method (not illustrated). With the use of the resist mask as a mask, portions of the semiconductor layers 184 a and 184 b, the conductive layer 185, and the layer 186 are selectively removed to form the semiconductor layer 109_1 a, the semiconductor layer 109_2 a 1, the semiconductor layer 109_2 a 2, the semiconductor layer 109_1 b, the semiconductor layer 109_2 b 1, the semiconductor layer 109_2 b 2, the electrode 110_1, the electrode 110_2 a, the electrode 110_2 b, the layer 128_1, the layer 128_2 a, and the layer 128_2 b (see FIG. 7B). At this time, a portion of the insulating layer 108 is also etched; thus, the insulating layer 108 has a projection.

The removal of the semiconductor layer 184 a, the semiconductor layer 184 b, the conductive layer 185, and the layer 186 can be performed by a dry etching method, a wet etching method, or the like. Both the dry etching method and the wet etching method may be used. The height of the projection can be adjusted by removal conditions (etching conditions) of the semiconductor layer 184 a, the semiconductor layer 184 b, the conductive layer 185, and the layer 186.

The introduction of impurities into the semiconductor layer 184 b which is described in Step 6 may be performed after Step 7.

[Step 8]

Next, heat treatment is preferably performed to reduce impurities such as moisture and hydrogen contained in the semiconductor layer 109 a and the semiconductor layer 109 b and to highly purify the semiconductor layer 109 a and the semiconductor layer 109 b.

Plasma treatment using an oxidizing gas may be performed before the heat treatment. For example, plasma treatment using a nitrous oxide gas is performed. By the plasma treatment, the fluorine concentration in the exposed insulating layer can be lowered. Moreover, the plasma treatment is effective in removing an organic substance on the surface of a sample.

For example, the heat treatment is performed in a reduced-pressure atmosphere, an inert gas atmosphere of nitrogen, a rare gas, or the like, an oxidizing gas atmosphere, or an ultra-dry air atmosphere (the moisture amount is 20 ppm (−55° C. by conversion into a dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less, in the case where the measurement is performed by a dew point meter in a cavity ring down laser spectroscopy (CRDS) system). Note that the oxidizing gas atmosphere refers to an atmosphere containing an oxidizing gas such as oxygen, ozone, or nitrogen oxide at 10 ppm or higher. The inert gas atmosphere refers to an atmosphere which contains the oxidizing gas at lower than 10 ppm and is filled with nitrogen or a rare gas.

By the heat treatment, at the same time that the impurities are released, oxygen contained in the insulating layer 108 is diffused to the semiconductor layer 109 a and the semiconductor layer 109 b and oxygen vacancies in the semiconductor layer 109 a and the semiconductor layer 109 b can be reduced. Note that the heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for desorbed oxygen. The heat treatment may be performed at any time after the semiconductor layer 184 b is formed. For example, the heat treatment may be performed after the formation of the layer 186.

The heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C. The treatment time is shorter than or equal to 24 hours. Heat treatment for over 24 hours is not preferable because the productivity is reduced.

In this embodiment, after heat treatment is performed at 400° C. in a nitrogen gas atmosphere for 1 hour, heat treatment is performed at 400° C. in an oxygen gas atmosphere for 1 hour. By performing the heat treatment in a nitrogen gas atmosphere first, impurities such as moisture or hydrogen contained in the semiconductor layer 109 a and the semiconductor layer 109 b are released, so that the impurity concentration in the semiconductor layers 109 a and 109 b is reduced. By performing the heat treatment in an oxygen gas atmosphere next, oxygen is introduced into the semiconductor layers 109 a and 109 b.

Note that in a CAAC-OS (described below), impurities or oxygen moves more easily in the a-axis direction and the b-axis direction than in the c-axis direction (film thickness direction). For example, in the case where the semiconductor layer is formed using a CAAC-OS, impurities are released mainly from a side surface of the semiconductor layer. Similarly, in the case where the semiconductor layer is formed using a CAAC-OS, oxygen is introduced mainly from the side surface of the semiconductor layer.

Since an upper surface of the electrode 110 is covered with the layer 128 at the heat treatment, oxidation caused from the upper surface can be prevented.

[Step 9]

A layer 187 is formed (see FIG. 7C). In this embodiment, the layer 187 is formed with the same composition and method as those of the layer 186. After the layer 187 is formed, oxygen doping treatment may be performed.

[Step 10]

A resist mask is formed over the layer 187 by a photolithography method (not illustrated). With the use of the resist mask as a mask, a portion of the layer 187 is selectively removed to form the layer 129_1 and the layer 129_2 (see FIG. 7D).

[Step 11]

The insulating layer 114 is formed, and a layer 121 is formed over the insulating layer 114 (see FIG. 8A). In this embodiment, a silicon oxynitride film is deposited as the insulating layer 114 by a CVD method. The insulating layer 114 is preferably an insulating layer containing excess oxygen. The insulating layer 114 may be subjected to oxygen doping treatment. The insulating layer 114 preferably has a flat surface. Thus, after the insulating layer 114 is formed, the surface of the insulating layer 114 may be subjected to CMP treatment to reduce roughness of the surface of the insulating layer 114. In this embodiment, a tungsten film is deposited as the layer 121.

[Step 12]

A portion of the layer 121 is selectively removed using a photolithography process, an etching process, and/or the like to form a hard mask 122 (see FIG. 8B).

[Step 13]

Portions of the insulating layer 114, the layers 129_1 and 128_1, and the electrode 110_1 are selectively removed using the hard mask 122 as a mask to form an opening 123 a. Furthermore, portions of the insulating layer 114, the layers 129_2 and 128_2, and the electrode 110_2 are selectively removed to form an opening 123 b (see FIG. 8C).

The opening 123 a includes a region overlapping with a portion of the semiconductor layer 109_1 b. In the opening 123 a, a portion of the semiconductor layer 109_1 b is exposed. In the step in which the opening 123 a is formed, the layer 129_1 a, the layer 129_1 b, the layer 128_1 a, the layer 128_1 b, the electrode 110_1 a, and the electrode 110_1 b are also formed.

The opening 123 b has a region overlapping with a portion of the semiconductor layer 109_2 b 1 and a region overlapping with a portion of the semiconductor layer 109_2 b 2. In the opening 123 b, portions of the semiconductor layers 109_2 b 1 and 109_2 b 2 are exposed. In the step in which the opening 123 b is formed, a portion of the layer 129_2 is removed, so that the 129_2 a and the layer 129_2 b are also formed.

Note that in this specification and the like, the opening 123 a and the opening 123 b may be collectively referred to as an “opening 123”.

The opening 123 is preferably formed by an anisotropic dry etching method so as to have a high aspect ratio (here, the ratio of the depth of the opening 123 to the width of the opening 123).

In the case of etching the conductive layer and the insulating layers by a dry etching method, a gas containing a halogen element can be used as an etching gas. As an example of the gas containing a halogen element, a chlorine-based gas such as chlorine (Cl₂), boron trichloride (BCl₃), silicon tetrachloride (SiCl₄), or carbon tetrachloride (CCl₄); a fluorine-based gas such as carbon tetrafluoride (CF₄), sulfur hexafluoride (SF₆), nitrogen trifluoride (NF₃), or trifluoromethane (CHF₃); hydrogen bromide (HBr), or oxygen can be used as appropriate. Furthermore, an inert gas may be added to an etching gas. As the etching gas used for etching of an oxide semiconductor, a mixed gas of an inert gas and a hydrocarbon-based gas such as methane (CH₄), ethane (C₂H₆), propane (C₃H₈), or butane (C₄H₁₀) may be used.

As a dry etching method, a parallel-plate-type reactive ion etching (RIE) method, an inductively coupled plasma (ICP) etching method, a dual frequency capacitively coupled plasma (DF-CCP) etching method, or the like can be used. In order to etch the film into a desired shape, the etching conditions (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on the substrate side, the temperature of the electrode on the substrate side, and the like) are adjusted as appropriate. Note that the formation of the opening 123 with the use of the hard mask 122 as a mask is preferably performed under etching conditions where the hard mask 122 is not easily etched.

As described above, the region 121 a of the semiconductor layer 109_1 b that is sandwiched between the electrode 110_1 a and the electrode 110_1 b can function as a channel formation region. The formation of the opening 123 exposes portions of the semiconductor layer 109_1 b, 109_2 b 1, and 109_2 b 2. Thus, depending on etching conditions, the exposed portions might be etched.

In the case where the opening 123 is formed by a dry etching method, an impurity element such as a residual component of the etching gas might be attached to the exposed surface of the semiconductor layer 109 b and the like. For example, when a chlorine-based gas is used as the etching gas, chlorine or the like might be attached. When a hydrocarbon-based gas is used as the etching gas, carbon, hydrogen, or the like might be attached.

Therefore, the impurity element attached to the exposed top and side surfaces of the semiconductor layers is preferably reduced after the opening 123 is formed. The impurity element may be reduced by, for example, cleaning treatment using a dilute hydrofluoric acid or the like, cleaning treatment using ozone or the like, or cleaning treatment using ultraviolet light or the like. Note that a plurality of types of cleaning treatment may be used in combination.

[Step 14]

A semiconductor layer 184 c and an insulating layer 124 are formed in this order (FIG. 9A). Although an example in which the semiconductor layer 184 c and the insulating layer 124 are formed in this order with the hard mask 122 left is described in this embodiment, the semiconductor layer 184 c and the insulating layer 124 may be formed after the hard mask 122 is removed.

In this embodiment, an oxide semiconductor containing much excess oxygen that is formed under the same conditions as those for forming the semiconductor layer 184 a is used for the semiconductor layer 184 c. Since the transmittance of oxygen in an oxide semiconductor depends on the composition, the composition of the oxide semiconductor to be used may be determined in accordance with the purpose as appropriate. For example, the semiconductor layer 184 c may be formed using a target having a composition of In:Ga:Zn=1:3:4. When a semiconductor layer containing excess oxygen is used as the semiconductor layer 184 c, oxygen can be supplied to the semiconductor layer 109_1 b by later heat treatment.

At the formation of the semiconductor layer 184 c, part of oxygen contained in the sputtering gas is supplied to the insulating layer 109_1 b in some cases, as in the case of the semiconductor layer 184 a. At the formation of the semiconductor layer 184 c, part of oxygen contained in the sputtering gas is supplied to the insulating layer 108 in some cases. Part of oxygen supplied to the insulating layer 108 reacts with hydrogen left in the insulating layer 108 to produce water and the water is released from the insulating layer 108 by later heat treatment. Thus, the hydrogen concentration in the insulating layer 108 can be reduced.

The semiconductor layer 184 c is formed along the side and bottom surfaces of the openings 123 a and 123 b. At this time, portions of the side surfaces of the semiconductor layer 109 a and portions of the side surfaces of the semiconductor layer 109 b are also covered with the semiconductor layer 184 c.

A silicon oxynitride film is deposited as the insulating layer 124 by a plasma CVD method (see FIG. 9A). The semiconductor layer 184 c may be subjected to oxygen doping treatment. Note that the insulating layer 124 may contain excess oxygen. The insulating layer 124 may be subjected to oxygen doping treatment.

[Step 15]

A conductive layer 125 is provided over the insulating layer 124 (see FIG. 9B). In this embodiment, a stack of tantalum nitride and tungsten is used as the conductive layer 125. Specifically, a tantalum nitride film is deposited over the insulating layer 124, and then, a tungsten film is deposited over tantalum nitride. The conductive layer 125 is preferably formed by, for example, an MOCVD method or the like. By using an MOCVD method or the like to form a conductor on a formation surface, the conductor can fill a depressed portion of the formation surface which has a high aspect ratio.

[Step 16]

CMP treatment is performed (see FIG. 9C), whereby portions of the conductive layer 125, the insulating layer 124, and the semiconductor layer 184 c are removed and the electrode 112, the insulating layer 111, and the semiconductor layer 109 c are formed. By CMP treatment, the hard mask 122 and a portion of the insulating layer 114 might be removed. The CMP treatment can reduce roughness of the sample surface, whereby coverage with an insulating layer or a conductive layer to be formed later can be increased.

As described above, the region 121 b of the semiconductor layer 109_2 c that is sandwiched between the semiconductor layer 109_2 b 1 and the semiconductor layer 109_2 b 2 when seen in the plan view can function as a channel formation region.

[Step 17]

Next, the insulating layer 115 is formed (see FIG. 10A). In this embodiment, an aluminum oxide film is formed as the insulating layer 115 by a sputtering method. At this time, part of oxygen used as a sputtering gas is introduced into the insulating layer 114, whereby a region 114 a containing excess oxygen is formed.

Part of excess oxygen in the insulating layer 114 reacts with hydrogen left in the insulating layer 114 to be water in some cases. Thus, after the insulating layer 115 is formed, the insulating layer 115 is removed and heat treatment is performed, so that hydrogen left in the insulating layer 114 can be released as water. By repeating the formation of the insulating layer 115, the removal of the insulating layer 115, and the heat treatment a plurality of times, the hydrogen concentration in the insulating layer 114 can be further reduced.

Furthermore, by performing oxygen doping treatment and heat treatment before the formation of the insulating layer 115, hydrogen left in the insulating layer 114 can be released as water. By repeating the oxygen doping treatment and the heat treatment a plurality of times, the hydrogen concentration in the insulating layer 114 can be further reduced.

After the formation of the insulating layer 115, oxygen doping treatment may be performed.

By providing the layers 128 and 129 and the semiconductor layer 109 c, oxygen in the insulating layer 114 can be less likely to be absorbed by the electrode 110 and the electrode 112. Thus, an increase in resistance of the electrodes 110 and 112 due to oxidation can be suppressed. Furthermore, the shortage of oxygen supplied to the semiconductor layer 109 can be prevented.

[Step 18]

A resist mask is formed over the sample surface by a photolithography method (not illustrated). With the use of the resist mask as a mask, portions of the insulating layers 115 and 114 and the layers 129 and 128 are removed to form an opening 192_1 a, an opening 192_1 b, an opening 192_2 a, and an opening 192_2 b (see FIG. 10B). Furthermore, portions of the insulating layer 115 are removed to form an opening 192_1 c and an opening 192_2 c (not illustrated).

The openings 192_1 a, 192_1 b, and 192_1 c overlap with the electrodes 110_1 a, 110_1 b, and 112_1, respectively. An exposed portion of the electrode 110_1 a is etched at the formation of the opening 192_1 a in some cases. An exposed portion of the electrode 110_1 b is etched at the formation of the opening 192_1 b in some cases. An exposed portion of the electrode 112_1 is etched at the formation of the opening 192_1 c in some cases.

The openings 192_2 a, 192_2 b, and 192_2 c overlap with the electrodes 110_2 a, 110_2 b, and 112_2, respectively. An exposed portion of the electrode 110_2 a is etched at the formation of the opening 192_2 a in some cases. An exposed portion of the electrode 110_2 b is etched at the formation of the opening 192_2 b in some cases. An exposed portion of the electrode 112_2 is etched at the formation of the opening 192_2 c in some cases.

[Step 19]

Next, a conductive layer 193 is formed (see FIG. 10C). In this embodiment, a stacked film of titanium nitride and tungsten is formed as the conductive layer 193 by an ALD method.

[Step 20]

CMP treatment is performed, whereby a portion of the conductive layer 193 is removed and the electrode 116_1 a, the electrode 1161 b, the electrode 116_2 a, and the electrode 116_2 b are formed (see FIG. 11A). At this time, a portion of a surface of the insulating layer 115 might also be removed.

[Step 21]

Next, a conductive layer 194 is formed (see FIG. 11B). In this embodiment, a tungsten film is deposited as the conductive layer 194 by a sputtering method.

[Step 22]

A resist mask is formed by a photolithography method (not illustrated). With the use of the resist mask as a mask, a portion of the conductive layer 194 is selectively removed to form the electrodes 117_1 a to 117_1 c (not illustrated) and the electrodes 117_2 a to 117_2 c (not illustrated) (see FIG. 11C). Note that when the electrode 117 is formed, part of the insulating layer 115 might be removed.

In such a manner, the transistors 100 and 200 having different structures can be provided over the same substrate through substantially the same process. By the above-described manufacturing method, the transistor 200 is not necessarily manufactured after the transistor 100 is manufactured, for example; thus, the productivity of the semiconductor device can be increased.

In the transistor 100, a channel is formed in the semiconductor layer 109_1 b in contact with the semiconductor layer 109_1 a and the semiconductor layer 109_1 c. In the transistor 200, a channel is formed in the semiconductor layer 109_2 c in contact with the insulating layer 108 and the insulating layer 111. Thus, the transistor 200 is likely to be affected by interface scattering compared with the transistor 100. In this embodiment, the electron affinity of the semiconductor layer 109_2 c is lower than that of the semiconductor layer 109_1 b. Thus, the transistor 200 has higher V_(th) than the transistor 100.

According to one embodiment of the present invention, transistors having different structures can be manufactured through substantially the same process. According to one embodiment of the present invention, a semiconductor device including transistors having different structures can be manufactured with high productivity. According to one embodiment of the present invention, a semiconductor device including transistors having different electrical characteristics can be manufactured with high productivity.

When insulating layers that are relatively impermeable to impurities and are formed using aluminum oxide or the like are provided over and under the transistors 100 and 200, impurity diffusion into the transistors 100 and 200 from the outside can be prevented, the operations of the transistors 100 and 200 can be stabilized, and the reliabilities thereof can be improved. In addition, when the insulating layers of aluminum oxide or the like that are relatively impermeable to oxygen are provided over and under the transistors 100 and 200, oxygen release can be prevented. Thus, the operations of the transistors 100 and 200 can be stabilized, and the reliabilities thereof can be improved. In addition, the electrical characteristics of the transistors can be improved.

The electrode 112, which can function as a gate electrode, of the transistor of one embodiment of the present invention is formed using a damascene process. Forming the gate electrode using a damascene process enables miniaturization and high density of the transistor. The positions of a channel formation region, a source region, and a drain region in a semiconductor layer of the transistor of one embodiment of the present invention are determined by formation of the opening 123. In other words, the positions of the channel formation region, the source region, and the drain region in the semiconductor layer are determined by a self-aligned process. Thus, the parasitic capacitances between the gate and the source and between the gate and the drain of the transistor of one embodiment of the present invention are small. One embodiment of the present invention can provide a transistor which performs high-speed operation and has low power consumption.

FIGS. 12A to 12C, FIGS. 13A to 13C, and FIGS. 14A to 14C illustrate modification examples of the semiconductor device 1000.

Modification Example 1

A semiconductor device 1000A illustrated in FIG. 12A includes a transistor 100A and a transistor 200A. The transistors 100A and 200A are different from the transistors 100 and 200 in the shape of the insulating layer 108. Depending on the processing conditions in Step 7, a portion of the insulating layer 108 is selectively removed to expose the insulating layer 107, so that an island-shaped insulating layer 108_1, an island-shaped insulating layer 108_2 a, and an island-shaped insulating layer 108_2 b can be provided.

Since the insulating layer 108 overlapping with the semiconductor layer 109_2 c is removed, the electrode 105_2 and the semiconductor layer 109_2 c can be close to each other. Thus, an effect of the electrode 105_2 used as a gate or a back gate can be enhanced.

Modification Example 2

A semiconductor device 1000B illustrated in FIG. 12B includes a transistor 100B and a transistor 200B. The transistors 100B and 200B are different from the transistors 100 and 200 in the shape of the semiconductor layer 129. The semiconductor device 1000B can be fabricated in the case where Step 10 described above is omitted and selective removal of the semiconductor layer 129 is not performed. Since the number of steps for manufacturing the semiconductor device 1000B can be smaller than that for manufacturing the semiconductor device 1000, the semiconductor device can be manufactured with high productivity.

Modification Example 3

A semiconductor device 1000C illustrated in FIG. 12C includes transistors 100C and 200C. The transistor 100C is different from the transistor 100 in that the insulating layer 106 and the insulating layer 107 are not formed. The transistor 200C is different from the transistor 200 in that the insulating layer 106 and the insulating layer 107 are not formed. The insulating layer 106 and the insulating layer 107 are not necessarily formed depending on the performance and use required for the semiconductor device. Not providing the insulating layer 106 and the insulating layer 107 can increase the productivity of the semiconductor device and allows the electrode 105 to be closer to the semiconductor layer 109. Thus, an effect that can be obtained when the electrode 105 is used as a gate or a back gate can be increased.

Modification Example 4

A semiconductor device 1000D illustrated in FIG. 13A includes the transistor 100 and a transistor 200D. The transistor 200D has the structure of the transistor 200 without the electrode 105_2. The electrode 105_2 is not necessarily formed, depending on the performance and use required for the semiconductor device.

Modification Example 5

A semiconductor device 1000E illustrated in FIG. 13B includes a transistor 100E and the transistor 200. The transistor 100E has the structure of the transistor 100 without the electrode 105_1. The electrode 105_1 is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device. Note that a structure where neither the electrode 105_1 nor the electrode 105_2 is provided can be employed.

Modification Example 6

A semiconductor device 1000F illustrated in FIG. 13C includes the transistor 100 and a transistor 200F. The transistor 200F has the structure of the transistor 200 without the electrode 112_2, the insulating layer 111_2, and the semiconductor layer 109_2 c. The transistor 200F can be fabricated in such a manner that the opening 123 b is not formed in Steps 12 and 13. Since the opening 123 b is not formed, the layer 129_2 is not separated into the layer 129_2 a and the layer 129_2 b. Furthermore, the electrode 112_2, the insulating layer 111_2, and the semiconductor layer 109_2 c are not formed. The electrode 112_2, the insulating layer 111_2, and the semiconductor layer 109_2 c are not necessarily formed depending on the performance and use required for the semiconductor device.

Modification Example 7

A semiconductor device 1000G illustrated in FIG. 14A includes transistors 100G and 200G. The transistors 100G and 200G are different from the transistors 100 and 200 in that the layer 128 is not provided. In the semiconductor device 1000G, the layer 186 is not formed in Step 6. After the semiconductor layer and the like are processed into an island shape in Step 7, heat treatment in Step 8 is skipped and the layer 187 is formed. The heat treatment in Step 8 is performed after formation of the layer 187. Furthermore, for the heat treatment in Step 8, a material that does not easily react with oxygen and/or does not easily absorb oxygen may be used for the electrode 110. Not providing the layer 128 can increase the productivity of the semiconductor device.

Modification Example 8

A semiconductor device 1000H illustrated in FIG. 14B includes the transistor 100 and a transistor 200H. The transistor 200H is different from the transistor 200 in including the semiconductor layer 109_2 a, in which the semiconductor layer 109_2 a 1 and the semiconductor layer 109_2 a 2 are continuous. In the transistor 200H, one or both of the semiconductor layer 109_2 a and the semiconductor layer 109_2 c can function as a semiconductor layer in which a channel is formed.

Modification Example 9

A semiconductor device 1000I illustrated in FIG. 14C includes transistors 100I and 200I. The transistor 100I and the transistor 200I are different from the transistor 100 and the transistor 200 in that the semiconductor layer 109 a is not provided. The semiconductor layer 109 a is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device. Not providing the semiconductor layer 109 a can increase the productivity of the semiconductor device.

This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments, Example, and the like.

Embodiment 2

In this embodiment, a semiconductor device 1010 having a different structure from that of the semiconductor device 1000 will be described with reference to drawings. In order to avoid repeated description, a description is mainly made on portions different from those of the semiconductor device 1000. The description of any of the other embodiments can be referred to for the portions that are not described in this embodiment.

<Structure Example of Semiconductor Device 1010>

FIG. 15A is a cross-sectional view of the semiconductor device 1010. The semiconductor device 1010 includes a transistor 150 and a transistor 250. The transistors 150 and 250 have different structures. FIG. 15A illustrates cross sections of the transistors 150 and 250 over the substrate 101. FIG. 15A corresponds to a cross-sectional view taken along dashed-dotted line L5-L6 in FIG. 16A and a cross-sectional view taken along dashed-dotted line L7-L8 in FIG. 17A.

FIGS. 15B and 15C each show a V_(g)-I_(d) curve, which is one of the electrical characteristics of a transistor. In the V_(g)-I_(d) curves in FIGS. 15B and 15C, the horizontal axis and the vertical axis represent voltage between a gate and a source (V_(g)) of the transistor and current flowing to a drain (I_(d)) of the transistor on a logarithmic scale, respectively.

The transistors 150 and 250 are each a transistor including a back gate. FIG. 15B shows the V_(g)-I_(d) curve of the transistor 150 when the potential of the back gate is set to the same as that of the source or the gate. FIG. 15C shows the V_(g)-I_(d) curve of the transistor 250 when the potential of the back gate is set to the same as that of the source or the gate. As shown in FIGS. 15B and 15C, the transistors 150 and 250 have different transistor characteristics. The V_(g) in the V_(g)-I_(d) curve of the transistor 250 is shifted in the positive direction compared with that in the V_(g)-I_(d) curve of the transistor 150. In other words, the transistor 250 has higher V_(th) than the transistor 150.

The transistors 150 and 250 will be described with reference to drawings.

[Transistor 150]

FIG. 16A is a plan view of the transistor 150. FIG. 16B is a cross-sectional view taken along dashed-dotted line L5-L6 and a cross-sectional view taken along dashed-dotted line W5-W6 in FIG. 16A. In FIG. 16B, the cross-sectional view along L5-L6 is taken in the channel length direction of the transistor 150 and the cross-sectional view along W5-W6 is taken in the channel width direction of the transistor 150. FIG. 16C is an enlarged view of a portion 134 in FIG. 16B.

The transistor 150 is a kind of top-gate transistor. The transistor 150 has substantially the same structure as the transistor 100 except that the layer 129_1 is not provided. The layer 129_1 is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device.

[Transistor 250]

FIG. 17A is a plan view of the transistor 250. FIG. 17B is a cross-sectional view taken along dashed-dotted line L7-L8 and a cross-sectional view taken along dashed-dotted line W7-W8 in FIG. 17A. In FIG. 17B, the cross-sectional view along L7-L8 is taken in the channel length direction of the transistor 250 and the cross-sectional view along W7-W8 is taken in the channel width direction of the transistor 250. FIG. 17C is an enlarged view of a portion 136 in FIG. 17B.

The transistor 250 is a kind of top-gate transistor. The transistor 250 has substantially the same structure as the transistor 200 except that the layer 129_2 is not provided. The layer 129_2 is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device. Not providing the layer 129 can increase the productivity of the semiconductor device.

<Example of Method for Manufacturing Semiconductor Device 1010>

An example of a method for manufacturing the semiconductor device 1010 will be described with reference to FIGS. 18A and 18B. An L5-L6 cross section in each of FIGS. 18A and 18B corresponds to the cross section taken along dashed-dotted line L5-L6 in FIG. 16A. An L7-L8 cross section in each of FIGS. 18A and 18B corresponds to the cross section taken along dashed-dotted line L7-L8 in FIG. 17A.

The steps up to Step 7 described in the above embodiment are performed, whereby the semiconductor layer 109_1 a, the semiconductor layer 109_2 a 1, the semiconductor layer 109_2 a 2, the semiconductor layer 109_1 b, the semiconductor layer 109_2 b 1, the semiconductor layer 109_2 b 2, the electrode 110_1, the electrode 110_2 a, the electrode 110_2 b, the layer 128_1, the layer 128_2 a, and the layer 128_2 b are formed (see FIG. 18A).

Next, heat treatment may be performed in a manner similar to that in Step 8 described in the above embodiment. In the manufacturing method described in this embodiment, Steps 9 and 10 described in the above embodiment are skipped, and Step 11 is performed (see FIG. 18B). The insulating layer 114 is formed in contact with the layer 128, and the layer 121 is formed over the insulating layer 114.

The subsequent steps can be performed in a manner similar to that of the steps including and after Step 12 described in the above embodiment.

Modification Example 1

A semiconductor device 1010A illustrated in FIG. 19A includes a transistor 150A and a transistor 250A. The transistors 150A and 250A are different from the transistors 150 and 250 in the shape of the insulating layer 108. Depending on the processing conditions in Step 7, a portion of the insulating layer 108 is selectively removed to expose the insulating layer 107, so that the island-shaped insulating layer 108_1, the island-shaped insulating layer 108_2 a, and the island-shaped insulating layer 108_2 b can be provided.

Since the insulating layer 108 overlapping with the region 121 b is removed, the electrode 105_2 and the semiconductor layer 109_2 c can be close to each other. Thus, the function of the electrode 105_2 used as a gate or a back gate can be enhanced.

Modification Example 2

A semiconductor device 1010B illustrated in FIG. 19B includes a transistor 150B and a transistor 250B. The transistor 150B is different from the transistor 150 in that the insulating layer 106 and the insulating layer 107 are not formed. The transistor 250B is different from the transistor 250 in that the insulating layer 106 and the insulating layer 107 are not formed. The insulating layer 106 and the insulating layer 107 are not necessarily formed depending on the performance and use required for the semiconductor device. Not providing the insulating layer 106 and the insulating layer 107 can increase the productivity of the semiconductor device and allows the electrode 105 to be closer to the semiconductor layer 109. Thus, an effect that can be obtained when the electrode 105 is used as a gate or a back gate can be increased.

Modification Example 3

A semiconductor device 1010C illustrated in FIG. 19C includes the transistor 150 and a transistor 250C. The transistor 250C has the structure of the transistor 250 without the electrode 105_2. The electrode 105_2 is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device.

Modification Example 4

A semiconductor device 1010D illustrated in FIG. 20A includes a transistor 150D and the transistor 250. The transistor 150D has the structure of the transistor 150 without the electrode 105_1. The electrode 105_1 is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device. Note that a structure where neither the electrode 105_1 nor the electrode 105_2 is provided can be employed.

Modification Example 5

A semiconductor device 1010E illustrated in FIG. 20B includes a transistor 150D and a transistor 250C. As in the semiconductor device 1010E, the electrode 105 is not necessarily provided depending on the performance and use required for the semiconductor device.

Modification Example 6

A semiconductor device 1010F illustrated in FIG. 20C includes a transistor 150F and a transistor 250F. The transistor 150F has the structure of the transistor 150 without the layer 128_1. The transistor 250F has the structure of the transistor 250 without the layer 128_2. The layer 128 is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device.

Modification Example 7

A semiconductor device 1010G illustrated in FIG. 21A includes the transistor 150 and a transistor 250G. The transistor 250G is different from the transistor 250 in including the semiconductor layer 109_2 a, in which the semiconductor layer 109_2 a 1 and the semiconductor layer 109_2 a 2 are continuous. In the transistor 250G, one or both of the semiconductor layer 109_2 a and the semiconductor layer 109_2 c can function as a semiconductor layer in which a channel is formed.

Modification Example 8

A semiconductor device 1010H illustrated in FIG. 21B includes a transistor 150H and a transistor 250H. The transistor 150H has the structure of the transistor 150 without the semiconductor layer 109_1 a. The transistor 250H has the structure of the transistor 250 without the semiconductor layer 109_2 a 1 and the semiconductor layer 109_2 a 2. The semiconductor layer 109 a is not necessarily provided, depending on the performance, purpose, or the like required for the semiconductor device.

This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments, Example, and the like.

Embodiment 3

In this embodiment, examples of a semiconductor device including any of the transistors disclosed in this specification and the like will be described.

<Structural Example of Semiconductor Device>

FIGS. 22A to 22C are cross-sectional views of a semiconductor device 400. The semiconductor device 400 includes the transistor 100 and a transistor 281. Note that the transistor 100 described in this embodiment can be replaced with any of the other transistors described in the above embodiments. FIG. 22A is a cross-sectional view of the transistor 100 and the transistor 281 in the channel length direction, and FIG. 22B is a cross-sectional view thereof in the channel width direction. FIG. 22C is an enlarged view of the transistor 281 in FIG. 22A.

In the semiconductor device 400, an n-type semiconductor is used for a substrate 401. The transistor 281 includes a channel formation region 283, high-concentration p-type impurity regions 285, an insulating layer 286, an electrode 287, and a sidewall 288. In regions overlapping with the sidewall 288 with the insulating layer 286 located therebetween, low-concentration p-type impurity regions 284 are provided. The insulating layer 286 can function as a gate insulating layer. The electrode 287 can function as a gate electrode. The channel formation region 283 of the transistor 281 is formed in part of the substrate 401.

The low-concentration p-type impurity regions 284 can be formed in such a manner that an impurity element is added with the use of the electrode 287 as a mask after the formation of the electrode 287 and before the formation of the sidewall 288. In other words, the low-concentration p-type impurity regions 284 can be formed in a self-aligned manner. After the sidewall 288 is formed, the high-concentration p-type impurity regions 285 are formed. Note that the low-concentration p-type impurity regions 284 have the same conductivity type as the high-concentration p-type impurity regions 285, and have a lower concentration of the impurity imparting the conductivity type than the high-concentration p-type impurity regions 285. The low-concentration p-type impurity regions 284 are not necessarily provided depending on circumstances.

The transistor 281 is electrically isolated from other transistors by an element isolation layer 414. The element isolation layer can be formed by a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like.

The transistor 281 can function as a p-channel transistor. An insulating layer 403 is formed over the transistor 281, and an insulating layer 404 is formed over the insulating layer 403. The insulating layer 403 and the insulating layer 404 can be formed using a material and a method which are similar to those of the insulating layer described in the above embodiment. Note that the insulating layer 403 and the insulating layer 404 are preferably formed using an insulating material that has a function of preventing diffusion of impurities such as oxygen, hydrogen, water, alkali metal, and alkaline earth metal. Note that one of the insulating layers 403 and 404 may be omitted or another insulating layer may be stacked thereover.

The semiconductor device 400 includes an insulating layer 405 having a flat surface over the insulating layer 404. The insulating layer 405 can be formed using a material and a method which are similar to those of the insulating layer described in the above embodiment. A surface of the insulating layer 405 may be subjected to CMP treatment.

A heat-resistant organic material such as a polyimide, an acrylic-based resin, a benzocyclobutene-based resin, a polyamide, or an epoxy-based resin may be used to form the insulating layer 405. Other than such organic materials, a low-dielectric constant material (a low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like may be used. Note that the insulating layer 405 may be formed by stacking a plurality of insulating layers formed using any of these materials.

An electrode 413 a, an electrode 413 b, and an electrode 413 c are formed over the insulating layer 405. The electrode 413 a, the electrode 413 b, and the electrode 413 c can be formed using a material and a method which are similar to those of the electrode described in the above embodiment.

The electrode 413 a is electrically connected to one of the high-concentration p-type impurity regions 285 through a contact plug 406 a. The electrode 413 b is electrically connected to the other of the high-concentration p-type impurity regions 285 through a contact plug 406 b. The electrode 413 c is electrically connected to the electrode 287 through a contact plug 406 c.

An insulating layer 407 is formed so as to cover the electrode 413 a, the electrode 413 b, and the electrode 413 c. The insulating layer 407 can be formed using a material and a method which are similar to those of the insulating layer 405. A surface of the insulating layer 407 may be subjected to CMP treatment.

The insulating layer 102 is formed over the insulating layer 407. Components over the insulating layer 407 can be understood with reference to the above embodiment. Thus, detailed description thereof is omitted in this embodiment. The electrode 117_1 b is electrically connected to the electrode 413 b through a contact plug 408.

The contact plugs 406 a, 406 b, 406 c, and 408 can be formed using a material and a method which are similar to those of the electrode 116.

Modification Example 1

A transistor 282 which is an n-channel transistor may be provided on the substrate 401. FIGS. 23A and 23B are cross-sectional views of a semiconductor device 410. The semiconductor device 410 includes the transistor 282 in addition to the components of the semiconductor device 400. FIG. 23A is a cross-sectional view of the transistor 100, the transistor 281, and the transistor 282 in the channel length direction, and FIG. 23B is an enlarged view of the transistor 282.

In the transistor 282, a channel formation region 1283 is formed in a well 220. The transistor 282 includes the channel formation region 1283, high-concentration n-type impurity regions 1285, the insulating layer 286, the electrode 287, and the sidewall 288. In regions overlapping with the sidewall 288 with the insulating layer 286 located therebetween, low-concentration n-type impurity regions 1284 are provided.

The low-concentration n-type impurity regions 1284 can be formed in such a manner that an impurity element is added with the use of the electrode 287 as a mask after the formation of the electrode 287 and before the formation of the sidewall 288. In other words, the low-concentration n-type impurity regions 1284 can be formed in a self-aligned manner. After the sidewall 288 is formed, the high-concentration n-type impurity regions 1285 are formed. Note that the low-concentration n-type impurity regions 1284 have the same conductivity type as the high-concentration n-type impurity regions 1285, and have a lower concentration of the impurity imparting the conductivity type than the high-concentration n-type impurity regions 1285. The low-concentration n-type impurity regions 1284 are not necessarily provided depending on circumstances.

Modification Example 2

FIGS. 24A to 24C are cross-sectional views of a semiconductor device 420. The semiconductor device 420 has a structure obtained by replacing the transistor 281 of the semiconductor device 400 with a FIN-type transistor 291. The effective channel width is increased in the FIN-type transistor, whereby the on-state characteristics of the transistor can be improved. In addition, since contribution of the electric field of the gate electrode to the channel formation region can be increased, the off-state characteristics of the transistor can be improved.

Modification Example 3

FIG. 25 is a cross-sectional view of a semiconductor device 430. The semiconductor device 430 includes the transistor 100, the transistor 200, the transistor 281, and a capacitor 240. In the semiconductor device 430, an insulating layer 431, an insulating layer 432, an insulating layer 433, an insulating layer 434, an insulating layer 435, and an insulating layer 436 are provided over the insulating layer 405 covering the transistor 281. Furthermore, an electrode 422 and an electrode 424 are provided over the insulating layer 405.

The electrode 422 is provided to be embedded in the insulating layers 431 and 432 and is electrically connected to the transistor 281 through an electrode 421 provided in the insulating layers 403 to 405.

The electrode 424 is provided to be embedded in the insulating layer 435 and is electrically connected to the electrode 422 through an electrode 423 provided in the insulating layers 433 and 434.

In the semiconductor device 430, the transistor 100 and the transistor 200 are provided over the insulating layer 436 with the insulating layers 102 and 103 located therebetween. The insulating layers 115 and 439 are provided over the transistor 100 and the transistor 200, and an electrode 427 and an electrode 241 are provided over the insulating layer 439. An insulating layer 242 covering the electrodes 427 and 241 is provided. Furthermore, an electrode 243 covering the electrode 241 is provided over the insulating layer 242.

A region where the electrode 241, the insulating layer 242, and the electrode 243 overlap with each other functions as the capacitor 240. By providing the electrode 243 to cover the electrode 241, not only a top surface but also side surfaces of the electrode 241 can function as the capacitor.

The electrode 427 is electrically connected to a source or a drain of the transistor 200 through an electrode 426 provided in portions of the insulating layers 439, 115, and 114, the semiconductor layer 109 c, and the layer 129.

An insulating layer 437 is provided over the electrode 243 and the insulating layer 242, an electrode 429 is provided over the insulating layer 437, and an insulating layer 438 is provided over the electrode 429. The electrode 429 is electrically connected to the electrode 427 through an electrode 428 provided in a portion of the insulating layer 437.

The insulating layers 431 to 439 and 242 can be formed using a material and a method which are similar to those of the insulating layers described in the above embodiments and the like. Furthermore, the electrodes 421 to 429, 241, and 243 can be formed using a material and a method which are similar to those of the electrodes described in the above embodiments and the like.

The electrodes 421 to 429 may be formed by a damascene method, a dual damascene method, or the like.

<Example of Semiconductor Circuit>

The transistors disclosed in this specification and the like can be used in a variety of semiconductor circuits, e.g., logic circuits such as an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit, an inverter circuit, a buffer circuit, a shift register circuit, a flip-flop circuit, an encoder circuit, a decoder circuit, an amplifier circuit, an analog switch circuit, an integration circuit, a differentiation circuit, and a memory element.

Examples of a semiconductor circuit including the transistor disclosed in this specification and the like are illustrated in circuit diagrams in FIGS. 26A to 26C. In the circuit diagrams and the like, “OS” is given beside the circuit symbol of a transistor which is preferably an OS transistor.

The semiconductor circuit illustrated in FIG. 26A has a configuration of an inverter circuit in which the p-channel transistor 281 and the n-channel transistor 282 are connected to each other in series and in which gates of the transistors are connected to each other.

The semiconductor circuit illustrated in FIG. 26B has a configuration of an analog switch circuit in which the p-channel transistor 281 and the n-channel transistor 282 are connected to each other in parallel.

The semiconductor circuit illustrated in FIG. 26C has a configuration of a NAND circuit including a transistor 281 a, a transistor 281 b, a transistor 282 a, and a transistor 282 b. A potential output from the NAND circuit depends on the combination of potentials input to an input terminal IN_A and an input terminal IN_B.

[Example of Memory Element]

The semiconductor circuit illustrated in FIG. 27A has a configuration of a memory element 251 a in which one of a source and a drain of a transistor 262 is connected to a gate of a transistor 263 and one electrode of a capacitor 258. The circuit illustrated in FIG. 27B has a configuration of a memory element 261 a in which one of the source and the drain of the transistor 262 is connected to one electrode of the capacitor 258.

The memory element 251 a and the memory element 261 a can each store charge injected through the wiring 254 and the transistor 262 at a node 257. The transistor 262 is an OS transistor, which enables charge to be stored at the node 257 for a long period.

The memory element 251 a includes the transistor 263. Although the transistor 263 is a p-channel transistor in FIG. 27A, the transistor 263 may be an n-channel transistor. For example, the transistor 281 or the transistor 282 may be used as the transistor 263. An OS transistor may also be used as the transistor 263.

The memory element 251 a in FIG. 27A and the memory element 261 a in FIG. 27B will be described in detail here.

The memory element 251 a includes the transistor 263 using a first semiconductor, the transistor 262 using a second semiconductor, and the capacitor 258.

As the transistor 262, the OS transistors disclosed in the above embodiment can be used. The use of such a transistor with a low off-state current as the transistor 262 enables data to be retained at the node 257 for a long period. In other words, power consumption of the memory element can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low.

In FIG. 27A, a wiring 252 is electrically connected to one of a source and a drain of the transistor 263, and a wiring 253 is electrically connected to the other of the source and the drain of the transistor 263. A wiring 255 is electrically connected to a gate of the transistor 262. One of the source and the drain of the transistor 262 is electrically connected to the node 257. The other of the source and the drain of the transistor 262 is electrically connected to the wiring 254. The gate of the transistor 263 and the one electrode of the capacitor 258 are electrically connected to the node 257. A wiring 256 is electrically connected to the other electrode of the capacitor 258.

The memory element 251 a illustrated in FIG. 27A has a feature that the charge supplied to the node 257 can be retained, and thus enables writing, retaining, and reading of data as follows.

[Writing and Retaining Operations]

Data writing and retaining operations of the memory element 251 a will be described. First, the potential of the wiring 255 is set to a potential at which the transistor 262 is on. Accordingly, the potential of the wiring 254 is supplied to the node 257. That is, a predetermined charge is supplied to the node 257 (writing). Here, one of two kinds of charges providing different potential levels (hereinafter also referred to as a “low-level charge” and a “high-level charge”) is supplied. After that, the potential of the wiring 255 is set to a potential at which the transistor 262 is off. Thus, the charge is retained at the node 257 (retaining operation).

Note that the high-level charge is a charge that supplies a higher potential to the node 257 than the low-level charge. In the case where the transistor 263 is a p-channel transistor, each of the high-level and low-level charges is a charge that supplies a potential higher than the threshold voltage of the transistor. In the case where the transistor 263 is an n-channel transistor, each of the high-level and low-level charges is a charge that supplies a potential lower than the threshold voltage of the transistor 263. In other words, each of the high-level and low-level charges is a charge that supplies a potential at which the transistor 263 is off.

[Reading Operation 1]

Next, data reading operation will be described. A reading potential V_(R) is supplied to the wiring 256 while a predetermined potential (a constant potential) different from the potential of the wiring 253 is supplied to the wiring 252, whereby data retained at the node 257 can be read.

The reading potential V_(R) is set to {(V_(th)−V_(H))+(V_(th)+V_(L))}/2, where V_(H) is the potential supplied in the case of the high-level charge and V_(L) is the potential supplied in the case of the low-level charge. Note that the potential of the wiring 256 in a period during which data is not read is set to a potential higher than V_(H) in the case where the transistor 263 is a p-channel transistor, and is set to a potential lower than V_(L) in the case where the transistor 263 is an n-channel transistor.

For example, in the case where the transistor 263 is a p-channel transistor, V_(R) is −2 V when V_(th) of the transistor 263 is −2 V, V_(H) is 1 V, and V_(L) is −1 V. When the potential written to the node 257 is V_(H) and V_(R) is applied to the wiring 256, V_(R)+V_(H), i.e., −1 V, is applied to the gate of the transistor 263. Since −1 V is higher than V_(th), the transistor 263 is not turned on. Thus, the potential of the wiring 253 is not changed. When the potential written to the node 257 is V_(L) and V_(R) is applied to the wiring 256, V_(R)+V_(L), i.e., −3 V, is applied to the gate of the transistor 263. Since −3 V is lower than V_(th), the transistor 263 is turned on. Thus, the potential of the wiring 253 is changed.

In the case where the transistor 263 is an n-channel transistor, V_(R) is 2 V when V_(th) of the transistor 263 is 2 V, V_(H) is −1 V, and V_(L) is −1 V. When the potential written to the node 257 is V_(H) and V_(R) is applied to the wiring 256, V_(R)+V_(H), i.e., 3 V, is applied to the gate of the transistor 263. Since 3 V is higher than V_(th), the transistor 263 is turned on. Thus, the potential of the wiring 253 is changed. When the potential written to the node 257 is V_(L) and V_(R) is applied to the wiring 256, V_(R)+V_(L), i.e., 1 V, is applied to the gate of the transistor 263. Since 1 V is lower than V_(th), the transistor 263 is not turned on. Thus, the potential of the wiring 253 is not changed.

By determining the potential of the wiring 253, data retained at the node 257 can be read.

The memory element 261 a illustrated in FIG. 27B is different from the memory element 251 a in that the transistor 263 is not provided. The other electrode of the capacitor 258 is electrically connected to a wiring 264. The potential of the wiring 264 may be any potential as long as it is a fixed potential. For example, the wiring 264 may be supplied with GND. Data can be written to the memory element 261 a in a manner similar to that of the memory element 251 a.

[Reading Operation 2]

Data reading operation of the memory element 261 a will be described. When a potential at which the transistor 262 is turned on is supplied to the wiring 255, the wiring 254 which is in a floating state and the capacitor 258 are brought into conduction, and the charge is redistributed between the wiring 254 and the capacitor 258. As a result, the potential of the wiring 254 is changed. The amount of change in the potential of the wiring 254 depends on the potential of the node 257 (or the charge accumulated in the node 257).

For example, the potential of the wiring 254 after the charge redistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potential of the node 257, C is the capacitance of the capacitor 258, C_(B) is the capacitance component of the wiring 254, and V_(B0) is the potential of the wiring 254 before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the node 257 is V₁ and V₀ (V₁>V₀), the potential of the wiring 254 in the case of retaining the potential V₁ (=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of the wiring 254 in the case of retaining the potential V₀ (=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the wiring 254 with a predetermined potential, data can be read.

When including a transistor using an oxide semiconductor and having an extremely low off-state current, the memory element described above can retain stored data for a long time. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).

In the memory element, a high voltage is not needed for data writing and deterioration of elements is unlikely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, the memory element of one embodiment of the present invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the on/off state of the transistor, whereby high-speed operation can be achieved.

The transistor 262 may be a transistor including a back gate. By controlling the potential supplied to the back gate, the threshold voltage of the transistor 262 can be appropriately changed. A memory element 251 b illustrated in FIG. 27C has substantially the same circuit configuration as the memory element 251 a. The memory element 251 b is different from the memory element 251 a in that a transistor including a back gate is used as the transistor 262. A memory element 261 b illustrated in FIG. 27D has substantially the same circuit configuration as the memory element 261 a. The memory element 261 b is different from the memory element 261 a in that a transistor including a back gate is used as the transistor 262.

In each of the memory elements 251 b and 261 b, the back gate of the transistor 262 is electrically connected to a wiring 259. By controlling the potential supplied to the wiring 259, the threshold voltage of the transistor 262 can be appropriately changed.

<Examples of Memory Device>

Examples of a memory device including any of the above memory elements are shown in circuit diagrams in FIGS. 28A and 28B. A memory device 300 illustrated in FIG. 28A includes a memory circuit 310 and a voltage retention circuit 320. A memory device 300 a illustrated in FIG. 28B includes a memory circuit 310 a and the voltage retention circuit 320 a. The memory circuits 310 and 310 a each include a plurality of memory elements. FIGS. 28A and 28B illustrate the case where three memory elements 261 b (memory elements 261 b_1 to 261 b_3) are provided.

In the memory device 300 illustrated in FIG. 28A, the memory element 261 b_1 included in the memory circuit 310 is electrically connected to a wiring 255_1 and a wiring 254_1. The memory element 261 b_2 included in the memory circuit 310 is electrically connected to a wiring 255_2 and a wiring 254_2. The memory element 261 b_3 included in the memory circuit 310 is electrically connected to a wiring 255_3 and a wiring 254_3. The memory elements 261 b_1 to 261 b_3 included in the memory circuit 310 are electrically connected to the wiring 264.

In the memory device 300 a illustrated in FIG. 28B, the memory elements 261 b_1 to 261 b_3 included in the memory circuit 310 a are electrically connected to the wiring 255. The memory element 261 b_1 included in the memory circuit 310 a is electrically connected to the wiring 254_1 and a wiring 264_1. The memory element 261 b_2 included in the memory circuit 310 a is electrically connected to the wiring 254_2 and a wiring 264_2. The memory element 261 b_3 included in the memory circuit 310 a is electrically connected to the wiring 254_3 and a wiring 264_3.

Note that the above description of the memory element 261 b can be referred to for structures, operations, and the like of the memory elements 261 b_1 to 261 b_3. Thus, detailed description is omitted here.

The voltage retention circuit 320 includes a transistor 323 and a capacitor 324. In FIG. 28A, the transistor 323 is a transistor including a back gate. One of a source and a drain of the transistor 323 is electrically connected to a terminal 321. The other of the source and the drain, a gate, and the back gate of the transistor 323 are electrically connected to the wiring 259. One electrode of the capacitor 324 is electrically connected to the wiring 259. The other electrode of the capacitor 324 is electrically connected to a wiring 322.

The voltage retention circuit 320 a includes a transistor 323 a and the capacitor 324. The transistor 323 a is different from the transistor 323 in not including a back gate. One of a source and a drain of the transistor 323 a is electrically connected to the terminal 321. The other of the source and the drain and a gate of the transistor 323 a are electrically connected to the wiring 259. One electrode of the capacitor 324 is electrically connected to the wiring 259. The other electrode of the capacitor 324 is electrically connected to the wiring 322.

In the memory devices 300 and 300 a, the potential of the wiring 259 can be changed by controlling the potential of the wiring 322. In the reading operation and the writing operation of the memory devices 300 and 300 a, a potential is supplied to the wiring 322 so that the potential of the wiring 259 is higher than a negative potential (a potential lower than GND) described later and lower than a potential corresponding to the V_(th) of the transistor 262 (a potential at which the transistor 262 is turned on).

In the case where gates of the transistors 262 in the memory elements 261 b_1 to 261 b_3 are electrically connected to the wiring 255 as in the memory device 300 a, the potential of the wiring 259 may be higher than or equal to a potential corresponding to the V_(th) of the transistor 262.

By controlling the potential of the wiring 259, the operation speed of the transistor 262 can be increased. Furthermore, the apparent V_(th) of the transistor 262 can be small. Thus, the data writing speed and the data reading speed can be increased.

In the retention operation of the memory circuit 310, a fixed potential is supplied to the wiring 322. For example, GND is supplied. After that, a negative potential (a potential lower than GND) is supplied to the terminal 321. When a negative potential is supplied to the terminal 321, the gate potential of the transistor 323 (transistor 323 a) becomes relatively high, so that the transistor 323 (transistor 323 a) is turned on. Consequently, the negative potential is supplied to the wiring 259 through the transistor 323 (transistor 323 a). More accurately, the wiring 259 is supplied with a potential higher than the negative potential by the V_(th) of the transistor 323 (transistor 323 a). Note that the wiring 259 is supplied with the negative potential in this embodiment for easy understanding.

When the wiring 259 is supplied with a negative potential, the potential of the back gate of the transistor 262 is decreased, and the transistor 262 is turned off; thus, data written to the memory circuit 310 can be retained. Furthermore, by supplying the negative potential to the back gate of the transistor 262, apparent V_(th) of the transistor is increased. Thus, even when the potential of the gate of the transistor 262 is changed, data written to the memory circuit 310 can be retained.

Next, a potential higher than or equal to GND is supplied to the terminal 321. For example, GND is supplied. Since the potential of the wiring 259 is a negative potential, the potential of the gate of the transistor becomes a negative potential. Accordingly, the transistor 323 (transistor 323 a) is turned off. Even when power supply to the memory device 300 (memory device 300 a) is stopped after that, the transistors 323 (323 a) and 262 can remain off.

The voltage retention circuit 320 has a function of suppressing a change in the potential of the wiring 259 in the retention operation of the memory device 300 (memory device 300 a). The voltage retention circuit 320 has a function of suppressing a change in the potential of the wiring 259 even when power supply to the memory device 300 (memory device 300 a) is stopped. In other words, the voltage retention circuit 320 has a function of retaining the voltage of the wiring 259. The transistor 323 (transistor 323 a) is preferably a transistor having a low off-state current because it retains the voltage of the wiring 259. For example, when the capacitance of the capacitor 324 is 10 pF and an acceptable increase in potential of the wiring 259 is 0.5 V, it takes an hour until the potential of the wiring 259 is increased by 0.5 V in the case where the off-state current of the transistor 323 (transistor 323 a) is 1.39×10⁻¹⁵ A, a day in the case where the off-state current of the transistor 323 (transistor 323 a) is 5.79×10⁻¹⁷ A, a year in the case where the off-state current of the transistor 323 (transistor 323 a) is 1.59×10⁻¹⁹ A, and ten years in the case where the off-state current of the transistor 323 (transistor 323 a) is 1.59×10⁻²⁰ A. When the off-state current of the transistor 323 (transistor 323 a) is lower than or equal to 1.59×10⁻²⁰ A, data written to the memory circuit 310 can be retained for ten years or more.

For example, by using an OS transistor as the transistor 323 (transistor 323 a), a transistor having an extremely low off-state current can be obtained. In order to reduce the off-state current, the transistor 323 (transistor 323 a) is preferably a transistor having a long channel length. Alternatively, the transistor 323 (transistor 323 a) is preferably a transistor with a short channel width. Alternatively, the transistor 323 (transistor 323 a) is preferably a transistor with a channel length longer than a channel width.

The transistor 323 (transistor 323 a) is particularly preferably a transistor having a low drain current (off-state current) at V_(g) of 0 V. Thus, a transistor having high V_(th) is preferably used as the transistor 323 (transistor 323 a). As the transistor having high V_(th), the transistor 200 or the like described above can be used.

As the transistor 262, which performs data writing and data reading, a transistor having a low V_(th) is preferably used. The drain current (off-state current) of the transistor 262 when V_(g) is 0 V is higher than that of the transistor 323 (the transistor 323 a) in some cases. As the transistor 262, a transistor having a high on-state current and high field-effect mobility is preferably used. Thus, the on-state current and field-effect mobility of the transistor 262 are higher than those of the transistor 323 (transistor 323 a) in some cases. As the transistor 262, the transistor 100 described above or the like can be used.

FIG. 29 illustrates part of a cross-sectional structure of the memory device 300 in the case where the transistor 100 is used as the transistor 262 of the memory circuit 310 and the transistor 200 is used as the transistor 323 of the voltage retention circuit 320.

In FIG. 29, the memory device 300 includes the transistor 262 and the transistor 323 over the substrate 101 with the insulating layers 102 and 103 provided therebetween; the insulating layer 115 and the insulating layer 439 over the transistors 262 and 323; the electrode 241, an electrode 244, and the electrode 427 over the insulating layer 439; the insulating layer 242 covering the electrodes 241, 244, and 427; and the electrode 243 covering the electrode 241 and an electrode 245 covering the electrode 244 over the insulating layer 242.

A region where the electrode 241, the insulating layer 242, and the electrode 243 overlap with each other functions as the capacitor 258. By providing the electrode 243 to cover the electrode 241, not only a top surface but also side surfaces of the electrode 241 can function as the capacitor. A region where the electrode 244, the insulating layer 242, and the electrode 245 overlap with each other functions as the capacitor 324. By providing the electrode 245 to cover the electrode 244, not only a top surface but also side surfaces of the electrode 244 can function as the capacitor.

The electrode 427 is electrically connected to one of a source and a drain of the transistor 323 through the electrode 426 provided in portions of the insulating layers 439, 115, and 114, the semiconductor layer 109 c, and the layer 129.

The insulating layer 437 is provided over the electrode 243, the electrode 245, and the insulating layer 242, the electrode 429 is provided over the insulating layer 437, and the insulating layer 438 is provided over the electrode 429. The electrode 429 is electrically connected to the electrode 427 through the electrode 428 provided in a portion of the insulating layer 437.

The other of the source and the drain of the transistor 323 is electrically connected to a gate of the transistor 323 and a back gate of the transistor 262. Although not illustrated, the gate and back gate of the transistor 323 are electrically connected to each other.

The insulating layers 439, 242, 437, and 438 can be formed using a material and a method which are similar to those of the insulating layers described in the above embodiment or the like. The electrodes 426, 427, 241, 243, 244, 245, 428, and 429 can be formed using a material and a method which are similar to those of the electrodes described in the above embodiment or the like. The electrodes 241, 244, and 427 can be formed through the same steps at the same time. The electrodes 243 and 245 can be formed through the same steps at the same time.

According to one embodiment of the present invention, transistors having different electrical characteristics can be manufactured through substantially the same process. That is, according one embodiment of the present invention, a memory device with high productivity can be provided. According to one embodiment of the present invention, a memory device which can retain data for a long period even when power supply is stopped can be provided. For example, a memory device which can retain data for a year or more, ten years or more after power supply is stopped can be provided. Thus, a memory device of one embodiment of the present invention can be regarded as a nonvolatile memory.

<Example of CPU>

Next, an example of a CPU including any of the above-described transistors and/or semiconductor devices will be described. FIG. 30 is a block diagram illustrating a configuration example of the CPU including any of the above-described transistors as a component.

The CPU illustrated in FIG. 30 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (BUS I/F), a rewritable ROM 1199, and a ROM interface (ROM I/F) 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 30 is just an example in which the configuration is simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in FIG. 30 or an arithmetic circuit is considered as one core; a plurality of the cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in response to the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 determines an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above circuits.

In the CPU illustrated in FIG. 30, a memory cell is provided in the register 1196. For the memory cell of the register 1196, any of the above-described transistors, the above-described memory device, or the like can be used.

In the CPU illustrated in FIG. 30, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or whether it is retained by a capacitor in the memory cell included in the register 1196. When data retaining by the flip-flop is selected, a power supply voltage is supplied to a memory element in the register 1196. When data retaining by the capacitor is selected, the data is rewritten in the capacitor, and supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

<Example of RF Tag>

Next, an example of an RF tag including any of the above-described transistors and/or semiconductor devices will be described. FIG. 31 is a block diagram illustrating a structure example of an RF tag.

The RF tag of one embodiment of the present invention includes a memory circuit (memory device), stores data in the memory circuit, and transmits and receives data to/from the outside with use of contactless means, for example, wireless communication. The RF tag with these features can be used for an individual authentication system in which an object or the like is recognized by reading the individual information, for example. In order that the RF tag is used for such application, high reliability is needed.

As shown in FIG. 31, an RF tag 800 includes an antenna 804 that receives a radio signal 803 that is transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader/writer, or the like). Any of the above-described transistors can be used for the communication device 801. The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. A transistor having a rectifying function included in the demodulation circuit 807 may be formed using a semiconductor that enables a reverse current to be low enough, for example, an oxide semiconductor. This can suppress reduction of a rectifying function due to generation of a reverse current and prevent saturation of the output from the demodulation circuit. In other words, the input to the demodulation circuit and the output from the demodulation circuit can have a relation closer to a linear relation. Note that data transmission methods are roughly classified into the following three methods: an electromagnetic coupling method in which a pair of coils is provided so as to face each other and communicates with each other by mutual induction, an electromagnetic induction method in which communication is performed using an induction field, and a radio wave method in which communication is performed using a radio wave. Any of these methods can be used in the RF tag 800.

Next, the configuration of each circuit will be described. The antenna 804 exchanges the radio signal 803 with the antenna 802 that is connected to the communication device 801. The rectifier circuit 805 generates an input potential by rectification, for example, half-wave voltage doubler rectification of an input alternating signal generated by reception of a radio signal at the antenna 804 and smoothing of the rectified signal with a capacitor in a later stage in the rectifier circuit 805. Note that a limiter circuit may be provided on an input side or an output side of the rectifier circuit 805. The limiter circuit controls electric power so that electric power that is higher than or equal to certain electric power is not input to a circuit in a later stage if the amplitude of the input alternating signal is high and an internal generation voltage is high.

The constant voltage circuit 806 generates a stable power supply voltage from an input potential and supplies it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit that generates a reset signal of the logic circuit 809 by utilizing rise of the stable power supply voltage.

The demodulation circuit 807 demodulates the input alternating signal by envelope detection and generates the demodulated signal. The modulation circuit 808 performs modulation in accordance with data to be output from the antenna 804.

The logic circuit 809 analyzes and processes the demodulated signal. The memory circuit 810 holds the input data and includes a row decoder, a column decoder, a memory region, and the like. The ROM 811 stores an identification number (ID) or the like and outputs it in accordance with processing.

Note that whether each circuit described above is provided can be determined as appropriate as needed.

Here, any of the semiconductor devices described above can be used as the memory circuit 810. Since the memory device of one embodiment of the present invention can retain data even when not powered, the memory device can be favorably used for an RF tag. In addition, the memory device of one embodiment of the present invention needs power (voltage) needed for data writing lower than that needed in a conventional nonvolatile memory; thus, it is possible to prevent a difference between the maximum communication range in data reading and that in data writing. Furthermore, it is possible to suppress malfunction or incorrect writing that is caused by power shortage in data writing.

Since the memory device of one embodiment of the present invention can be used as a nonvolatile memory, it can also be used as the ROM 811. In this case, it is preferable that a manufacturer separately prepare a command for writing data to the ROM 811 so that a user cannot rewrite data freely. Since the manufacturer gives identification numbers before shipment and then starts shipment of products, instead of putting identification numbers to all the manufactured RF tags, putting identification numbers only to good products to be shipped is possible. Thus, the identification numbers of the shipped products are in series and customer management corresponding to the shipped products is easily performed.

Application examples of an RF tag of one embodiment of the present invention will be described with reference to FIGS. 32A to 32F. The RF tag is widely used and can be provided for, for example, products, e.g., bills, coins, securities, bearer bonds, documents such as driver's licenses or resident's cards (see FIG. 32A), recording media such as DVD software or video tapes (see FIG. 32B), containers such as plates, cups, or bottles (see FIG. 32C), packaging containers such as wrapping paper, boxes, or ribbon, moving objects such as bicycles (see FIG. 32D), personal belongings such as bags or glasses, plants, animals, human bodies, clothing, household goods, medical supplies such as medicine and chemicals, and electronic devices (e.g., liquid crystal display devices, EL display devices, television sets, or cellular phones), or tags on products (see FIGS. 32E and 32F).

An RF tag 800 of one embodiment of the present invention is fixed to a product by being attached to a surface thereof or embedded therein. For example, the RF tag 800 is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. Since the RF tag 800 of one embodiment of the present invention can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Furthermore, a bill, a coin, a security, a bearer bond, a document, or the like can have an identification function by being provided with the RF tag 800 of one embodiment of the present invention, and the identification function can be utilized to prevent counterfeiting. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag 800 of one embodiment of the present invention for a packaging container, a recording medium, a personal belonging, clothing, household goods, an electronic appliance, or the like. A moving object can also have a higher level of security against theft or the like by being provided with the RF tag 800 of one embodiment of the present invention. As in the above cases, the RF tag 800 of one embodiment of the present invention can be used for a variety of applications.

<Imaging Device>

Next, an example of an imaging device which can include any of the above-described transistors or semiconductor devices will be described. In this embodiment, an imaging device 610 will be described with reference to drawings.

FIG. 33A is a plan view illustrating a configuration example of the imaging device 610. The imaging device 610 includes a pixel portion 640, a first circuit 660, a second circuit 670, a third circuit 680, and a fourth circuit 690. In this specification and the like, the first circuit 660 to the fourth circuit 690 and the like may be referred to as a “peripheral circuit” or a “driver circuit”. For example, the first circuit 660 can be regarded as part of the peripheral circuit.

FIG. 33B illustrates a configuration example of the pixel portion 640. The pixel portion 640 includes, for example, a plurality of pixels 645 (imaging elements) arranged in a matrix with p columns and q rows (p and q are each an integer greater than or equal to 2). Note that in FIG. 33B, n is a natural number of greater than or equal to 1 and smaller than or equal to p, and m is a natural number of greater than or equal to 1 and smaller than or equal to q.

For example, using the pixels 645 arranged in a 1920×1080 matrix, the imaging device 610 can be obtained which can take an image with “full high definition” (also referred to as “2K resolution”, “2K1K”, “2K”, and the like). Using the pixels 645 arranged in a 4096×2160 matrix, the imaging device 610 can be obtained which can take an image with “ultra-high definition” (also referred to as “4K resolution”, “4K2K”, “4K”, and the like). Using the pixels 645 arranged in a 8192×4320 matrix, the imaging device 610 can be obtained which can take an image with “super high definition” (also referred to as “8K resolution”, “8K4K”, “8K”, and the like). Using a larger number of pixels 645, the imaging device 610 can be obtained which can take an image with 16K or 32K resolution.

The first circuit 660 and the second circuit 670 are connected to the plurality of pixels 645 and have a function of supplying signals for driving the plurality of pixels 645. The first circuit 660 may have a function of processing an analog signal output from the pixel 645. The third circuit 680 may have a function of controlling the operation timing of the peripheral circuit. For example, the third circuit 680 may have a function of generating a clock signal. Furthermore, the third circuit 680 may have a function of converting the frequency of a clock signal supplied from the outside. Moreover, the third circuit 680 may have a function of supplying a reference potential signal (e.g., a ramp wave signal).

FIG. 34 is a configuration example of the first circuit 660. The first circuit 660 illustrated in FIG. 34 includes a signal processing circuit 661, a column driver circuit 662, and an output circuit 663. The signal processing circuit 661 includes a circuit 664 provided in each column. The circuit 664 includes a circuit 664 a which can remove noise by a correlated double sampling (CDS) method (also referred to as a “CDS circuit”), a counter circuit 664 b, and a latch circuit 664 c. The circuit 664 has a function of analog-digital conversion. The signal processing circuit 661 can function as a column-parallel (column type) analog-digital conversion device.

The circuit 664 a includes a comparator, a switch, and a capacitor. Two input terminals of the comparator are connected to each other via the switch. As the switch, a transistor, a microelectromechanical systems (MEMS) element, or the like may be used. One terminal of the comparator is connected to a wiring 667 via the capacitor. The other terminal of the comparator is connected to a wiring 623 which is provided in each column. Note that the other terminal of the comparator and the wiring 623 may be connected to each other via a capacitor.

The circuit 664 a has a function of comparing the potential of an analog signal (imaging data) input from the wiring 623 with that of a reference potential signal (e.g., a ramp wave signal) input from the wiring 667 and outputting an H potential or an L potential. A clock signal from a wiring 668 and the H potential or the L potential output from the circuit 664 a are input to the counter circuit 664 b. The counter circuit 664 b measures the length of a period in which the H potential or the L potential is input and outputs the measurement result to the latch circuit 664 c as an N-bit digital signal. A set signal or a reset signal is input from a wiring 665 to the counter circuit 664 b. The latch circuit 664 c has a function of holding the digital signal. A set signal or a reset signal is input from a wiring 666 to the latch circuit 664 c.

The column driver circuit 662 is also referred to as a column selection circuit, a horizontal driver circuit, or the like. The column driver circuit 662 generates a selection signal for selecting a column from which the imaging data held in the latch circuit 664 c is to be read. The column driver circuit 662 can be formed using a shift register or the like. Columns are sequentially selected by the column driver circuit 662, and the imaging data output from the latch circuit 664 c in the selected column is input to the output circuit 663 via a wiring 669. The wiring 669 can function as a horizontal transfer line.

The imaging data input to the output circuit 663 is processed in the output circuit 663, and is output to the outside of the imaging device 610. The output circuit 663 can be formed using a buffer circuit, for example. The output circuit 663 may have a function of controlling the timing at which a signal is output to the outside of the imaging device 610.

The second circuit 670 has a function of generating and outputting a selection signal for selecting the pixel 645 from which a signal is read. Note that the second circuit 670 may also be referred to as a row selection circuit or a vertical driver circuit. In this manner, imaging data which is an analog signal can be converted to an N-bit digital signal to be output to the outside.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a converter circuit. A semiconductor device such as an IC chip may be used as part or the whole of the peripheral circuit. Furthermore, the semiconductor device of one embodiment of the present invention may be provided in part of the peripheral circuit.

Note that in the peripheral circuit, at least one of the first circuit 660 to the fourth circuit 690 may be omitted. For example, when one of the first circuit 660 and the fourth circuit 690 additionally has a function of the other of the first circuit 660 and the fourth circuit 690, the other of the first circuit 660 and the fourth circuit 690 may be omitted. For another example, when one of the second circuit 670 and the third circuit 680 additionally has a function of the other of the second circuit 670 and the third circuit 680, the other of the second circuit 670 and the third circuit 680 may be omitted. As another example, a function of another peripheral circuit may be added to one of the first to fourth circuits 660 to 690 to omit that peripheral circuit.

As illustrated in FIGS. 35A and 35B, the pixel portion 640 may be provided over the first circuit 660 to the fourth circuit 690 to overlap with the first circuit 660 to the fourth circuit 690. FIG. 35A is a top view of the imaging device 610 in which the pixel portion 640 is provided over the first circuit 660 to the fourth circuit 690 to overlap with the first circuit 660 to the fourth circuit 690. FIG. 35B is a perspective view illustrating the structure of the imaging device 610 illustrated in FIG. 35A.

The provision of the pixel portion 640 over the first circuit 660 to the fourth circuit 690 can increase the area occupied by the pixel portion 640 in the imaging device 610. Accordingly, the light sensitivity, the dynamic range, the resolution, the quality of a captured image, or the integration degree of the imaging device 610 can be improved.

[Pixel (Imaging Element)]

Next, an example of a circuit which can be used for the pixel 645 will be described. The pixel 645 illustrated in FIG. 36A includes a photoelectric conversion element 638, a transistor 612, a transistor 635, and a capacitor 633. One of a source and a drain of the transistor 612 is electrically connected to the photoelectric conversion element 638. The other of the source and the drain of the transistor 612 is electrically connected to a gate of the transistor 635 via a node 637 (charge accumulation portion).

The transistor 100 and/or the transistor 200 or the like described in the above embodiments may be used as the transistor 612 and/or the transistor 635. For example, the transistor 200 may be used as the transistor 612. For example, the transistor 100 may be used as the transistor 612.

An OS transistor is preferably used as the transistor 612. Since the off-state current of the OS transistor is extremely low, the capacitor 633 can be small. Alternatively, the capacitor 633 can be omitted as in the pixel 645 illustrated in FIG. 36B. Furthermore, when the transistor 612 is an OS transistor, the potential of the node 637 is less likely to be changed. Thus, an imaging device which is less likely to be affected by noise can be provided. As the transistor 612, any of the transistors disclosed in the above embodiments, or the like, can be used. Note that the transistor 635 may be an OS transistor.

A diode element formed using a silicon substrate with a PN junction or a PIN junction can be used as the photoelectric conversion element 638. Alternatively, a PIN diode element formed using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. Alternatively, a diode-connected transistor may be used. Still alternatively, a variable resistor or the like utilizing a photoelectric effect may be formed using silicon, germanium, selenium, or the like.

The photoelectric conversion element may be formed using a material capable of generating charge by absorbing radiation. Examples of the material capable of generating charge by absorbing radiation include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

In the pixel 645 illustrated in FIG. 36C, a photodiode is used as the photoelectric conversion element 638. The pixel 645 illustrated in FIG. 36C includes the photoelectric conversion element 638, the transistor 612, a transistor 634, the transistor 635, a transistor 636, and the capacitor 633. One of the source and the drain of the transistor 612 is electrically connected to a cathode of the photoelectric conversion element 638. The other of the source and the drain of the transistor 612 is electrically connected to the node 637. An anode of the photoelectric conversion element 638 is electrically connected to a wiring 611. One of a source and a drain of the transistor 634 is electrically connected to the node 637. The other of the source and the drain of the transistor 634 is electrically connected to a wiring 618. The gate of the transistor 635 is electrically connected to the node 637. One of a source and a drain of the transistor 635 is electrically connected to a wiring 619. The other of the source and the drain of the transistor 635 is electrically connected to one of a source and a drain of the transistor 636. The other of the source and the drain of the transistor 636 is electrically connected to the wiring 618. One electrode of the capacitor 633 is electrically connected to the node 637. The other electrode of the capacitor 633 is electrically connected to the wiring 611.

The transistor 612 can function as a transfer transistor. A gate of the transistor 612 is supplied with a transfer signal TX. The transistor 634 can function as a reset transistor. A gate of the transistor 634 is supplied with a reset signal RST. The transistor 635 can function as an amplifier transistor. The transistor 636 can function as a selection transistor. A gate of the transistor 636 is supplied with a selection signal SEL. Moreover, V_(DD) is supplied to the wiring 618 and V_(SS) is supplied to the wiring 611.

Next, operations of the pixel 645 illustrated in FIG. 36C will be described. First, the transistor 634 is turned on so that V_(DD) is supplied to the node 637 (reset operation). Then, the transistor 634 is turned off so that V_(DD) is retained at the node 637. Next, the transistor 612 is turned on so that the potential of the node 637 is changed in accordance with the amount of light received by the photoelectric conversion element 638 (accumulation operation). After that, the transistor 612 is turned off so that the potential of the node 637 is retained. Next, the transistor 636 is turned on so that a potential corresponding to the potential of the node 637 is output to the wiring 619 (selection operation). Measuring the potential of the wiring 619 can determine the amount of light received by the photoelectric conversion element 638.

An OS transistor is preferably used as each of the transistors 612 and 634. Since the off-state current of the OS transistor is extremely low as described above, the capacitor 633 can be small or omitted. Furthermore, when the transistors 612 and 634 are OS transistors, the potential of the node 637 is less likely to be changed. Thus, an imaging device which is less likely to be affected by noise can be provided.

FIG. 37 illustrates a structure example of the pixel 645. FIG. 37 is a cross-sectional view of the pixel 645. In the pixel 645 illustrated in FIG. 37, an n-type semiconductor is used for the substrate 401. A p-type semiconductor 621 of the photoelectric conversion element 638 is provided in the substrate 401. A portion of the substrate 401 functions as an n-type semiconductor 622 of the photoelectric conversion element 638.

The transistor 635 is provided on the substrate 401. The transistor 635 can function as an n-channel transistor. A well 620 of a p-type semiconductor is provided in a portion of the substrate 401. The well 620 can be provided by a method similar to that for forming the p-type semiconductor 621. The well 620 and the p-type semiconductor 621 can be formed at the same time. Note that the transistor 282 described above can be used as the transistor 635, for example.

An insulating layer 613, an insulating layer 614, and an insulating layer 615 are formed over the photoelectric conversion element 638 and the transistor 635. The insulating layers 613 to 615 can be formed using a material and a method which are similar to those of the other insulating layers described above.

An opening 624 is formed in the insulating layers 613 to 615 so as to overlap with the n-type semiconductor 622, and an opening 625 is formed in the insulating layers 613 to 615 to overlap with the p-type semiconductor 621. Contact plugs 626 are formed in the opening 624 and the opening 625. The contact plugs 626 can be provided in a manner similar to that of the above-described contact plug. The number of openings (624 and 625) to be formed or their arrangement are not particularly limited. Thus, an imaging device with high layout flexibility can be provided.

An electrode 641, an electrode 642, and an electrode 629 are formed over the insulating layer 615. The electrode 641 is electrically connected to the n-type semiconductor 622 via the contact plug 626 provided in the opening 624. The electrode 629 is electrically connected to the p-type semiconductor 621 via the contact plug 626 provided in the opening 625.

An insulating layer 627 is formed so as to cover the electrode 641, the electrode 642, and the electrode 629. The insulating layer 627 can be formed using a material and a method which are similar to those of the insulating layer 615. A surface of the insulating layer 627 may be subjected to CMP treatment. By the CMP treatment, roughness of the surface can be reduced, and coverage with an insulating layer or a conductive layer formed later can be increased. The electrode 641, the electrode 642, and the electrode 629 can be formed using a material and a method which are similar to those of the above-described electrode.

The insulating layer 102 and the insulating layer 103 are formed over the insulating layer 627, and an electrode 418, an electrode 647, and an electrode 643 are formed over the insulating layer 103. The electrode 418 can function as a back gate of the transistor 612. The electrode 643 is electrically connected to the electrode 642 through an opening provided in the insulating layer 627, the insulating layer 102, and the insulating layer 103. The electrode 647 is electrically connected to the electrode 629 through an opening provided in the insulating layer 627, the insulating layer 102, and the insulating layer 103.

The electrodes 418, 647, and 643 can be formed using a material and a method which are similar to those of the above-described electrode. For example, the electrodes 418, 647, and 643 can be formed using a material and a method which are similar to those of the electrode 105. The electrodes 418, 647, and 643 may be formed by a damascene method, a dual damascene method, or the like. Note that FIG. 37 illustrates an example where the electrodes 418, 647, and 643 are formed using a stack of conductive layers.

The insulating layers 106, 107, 108, 114, and 115 are stacked in this order over the electrodes 418, 647, and 643 and the insulating layer 104. The transistor 612 is formed between the insulating layers 103 and 115. As the transistor 612, the transistor 100 or 200 or the like described in the above embodiments may be used. FIG. 37 illustrates an example where the transistor 100 is used as the transistor 612.

An insulating layer 477 is formed over the insulating layer 115, and an electrode 644 and the electrode 631 are formed over the insulating layer 477. An insulating layer 639 is formed to cover the electrode 644 and the electrode 631. An electrode 632 is formed to cover the electrode 631 with the insulating layer 639 provided therebetween. A region where the electrode 631, the insulating layer 639, and the electrode 632 overlap with each other functions as the capacitor 633.

The electrode 644 is electrically connected to one of the source and the drain of the transistor 612. The electrode 644 is electrically connected to the electrode 647.

The insulating layer 437 is formed over the electrode 632.

Modification Example 1

FIG. 38 illustrates a structure example of the pixel 645 that is different from that in FIG. 37.

In the pixel 645 illustrated in FIG. 38, the transistor 635 and the transistor 636 are provided on the substrate 401. The transistor 635 can function as an n-channel transistor. The transistor 636 can function as a p-channel transistor. The transistor 635 and the transistor 636 are electrically isolated from each other by the element isolation layer 414. Note that the transistor 282 described above can be used as the transistor 635, for example. The transistor 281 described above can be used as the transistor 636, for example.

The electrode 413 a, the electrode 413 b, the electrode 413 c, and an electrode 413 d are formed over the insulating layer 615. The electrode 413 a is electrically connected to one of the source and the drain of the transistor 635, and the electrode 413 b is electrically connected to the other of the source and the drain of the transistor 635. The electrode 413 c is electrically connected to the gate of the transistor 635. The electrode 413 b is electrically connected to one of the source and the drain of the transistor 636, and the electrode 413 d is electrically connected to the other of the source and the drain of the transistor 636. The electrodes 413 a to 413 d can be formed using a material and a method which are similar to those of the above-described electrode.

In the pixel 645 illustrated in FIG. 38, the photoelectric conversion element 638 is provided over the insulating layer 437. An insulating layer 617 is provided over the photoelectric conversion element 638, and an electrode 488 is provided over the insulating layer 617. The insulating layer 617 can be formed using a material and a method which are similar to those of the insulating layer 437.

The photoelectric conversion element 638 illustrated in FIG. 38 includes a photoelectric conversion layer 681 between an electrode 686 formed with a metal material or the like and a light-transmitting conductive layer 682. FIG. 38 illustrates the photoelectric conversion element 638 including a selenium-based material for the photoelectric conversion layer 681. The photoelectric conversion element 638 including a selenium-based material has high external quantum efficiency with respect to visible light. Moreover, the use of the photoelectric conversion element enables fabrication of a highly sensitive sensor in which the amplification of electrons with respect to the amount of incident light is large owing to an avalanche phenomenon. Furthermore, the selenium-based material has a high light-absorption coefficient, which leads to an advantage that the photoelectric conversion layer 681 can be formed thin.

Amorphous selenium or crystalline selenium can be used as the selenium-based material. Crystalline selenium can be obtained by, for example, depositing amorphous selenium and then performing heat treatment. When the crystal grain size of crystalline selenium is smaller than a pixel pitch, variation in characteristics between pixels can be reduced. Moreover, crystalline selenium has higher spectral sensitivity and light-absorption coefficient for visible light than amorphous selenium.

Although the photoelectric conversion layer 681 is illustrated as a single layer, gallium oxide, cerium oxide, or the like as a hole injection blocking layer may be provided on the light reception side of the selenium-based material, and nickel oxide, antimony sulfide, or the like as an electron injection blocking layer may be provided on the electrode 686 side.

Furthermore, the photoelectric conversion layer 681 may be a layer including a compound of copper, indium, and selenium (CIS). Alternatively, a layer including a compound of copper, indium, gallium, and selenium (CIGS) may be used. With CIS or CIGS, a photoelectric conversion element that can utilize an avalanche phenomenon as in the case of using a single layer of selenium can be formed.

Furthermore, CIS and CIGS are p-type semiconductors, and an n-type semiconductor such as cadmium sulfide or zinc sulfide may be provided in contact with the p-type semiconductor in order to form a junction.

It is preferable to apply a relatively high voltage (e.g., 10 V or higher) to the photoelectric conversion element in order to cause the avalanche phenomenon. Since the OS transistor has higher drain withstand voltage than a Si transistor, the application of a relatively high voltage to the photoelectric conversion element is easy. Thus, by the combined use of the OS transistor having high drain withstand voltage and a photoelectric conversion element including the selenium-based material in the photoelectric conversion layer, a highly sensitive and highly reliable imaging device can be obtained.

For the light-transmitting conductive layer 682, the following can be used: indium tin oxide; indium tin oxide containing silicon; indium oxide containing zinc; zinc oxide; zinc oxide containing gallium; zinc oxide containing aluminum; tin oxide; tin oxide containing fluorine; tin oxide containing antimony; graphene; or the like. The light-transmitting conductive layer 682 is not limited to a single layer, and may be a stacked layer of different films. Although the light-transmitting conductive layer 682 and a wiring 487 are electrically connected to each other through the electrode 488 and a contact plug 489 in the structure illustrated in FIG. 38, the light-transmitting conductive layer 682 and the wiring 487 may be in direct contact with each other.

The electrode 686, the wiring 487, and the like may each have a structure in which a plurality of conductive layers are stacked. For example, the electrode 686 can include a first conductive layer and a second conductive layer, and the wiring 487 can include a third conductive layer and a fourth conductive layer (not illustrated). For example, the first conductive layer and the third conductive layer may be made of a low-resistance metal or the like, and the second conductive layer and the fourth conductive layer may be made of a metal or the like that exhibits an excellent contact property with the photoelectric conversion layer 681. Such a structure improves the electrical properties of the photoelectric conversion element. Note that some kinds of metal may cause electrochemical corrosion by being in contact with the light-transmitting conductive layer 682. Even when such a metal is used in the third conductive layer, electrochemical corrosion can be prevented by the fourth conductive layer.

The second conductive layer and the fourth conductive layer can be formed using, for example, molybdenum, tungsten, or the like. The first conductive layer and the third conductive layer can be formed using, for example, aluminum, titanium, or a stack of titanium, aluminum, and titanium that are stacked in this order.

The insulating layer 617 may be a multilayer. Note that a partition wall 677 can be formed using an inorganic insulator, an insulating organic resin, or the like. The partition wall 677 may be colored black or the like in order to shield the transistors and the like from light and/or to determine the area of a light-receiving portion in each pixel.

Alternatively, a PIN diode element or the like formed using an amorphous silicon film, a microcrystalline silicon film, or the like may be used as the photoelectric conversion element 638. In the photodiode, an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer are stacked in this order. The i-type semiconductor layer is preferably formed using amorphous silicon. The p-type semiconductor layer and the n-type semiconductor layer can each be formed using amorphous silicon, microcrystalline silicon, or the like that includes a dopant imparting the corresponding conductivity type. A photodiode in which a photoelectric conversion layer is formed using amorphous silicon has high sensitivity in a visible light wavelength region, and therefore can easily sense weak visible light.

Note that a PN or PIN diode element is preferably provided such that the p-type semiconductor layer serves as a light-receiving surface, in which case the output current of the photoelectric conversion element 638 can be increased.

The photoelectric conversion element 638 formed using the selenium-based material, amorphous silicon, or the like can be formed through general semiconductor manufacturing processes such as a deposition process, a lithography process, and an etching process.

<Semiconductor Wafer and Chip>

FIG. 39A is a top view illustrating a substrate 711 before dicing treatment. As the substrate 711, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used, for example. A plurality of circuit regions 712 are provided over the substrate 711. A semiconductor device, a CPU, an RF tag, or an imaging device, according to one embodiment of the present invention, or the like can be provided in the circuit region 712.

The plurality of circuit regions 712 are each surrounded by a separation region 713. Separation lines (also referred to as “dicing lines”) 714 are set at a position overlapping with the separation regions 713. The substrate 711 can be cut along the separation lines 714 into chips 715 including the circuit regions 712. FIG. 39B is an enlarged view of the chip 715.

A conductive layer or a semiconductor layer may be provided in the separation regions 713. Providing a conductive layer or a semiconductor layer in the separation regions 713 relieves ESD that might be caused in a dicing step, preventing a decrease in the yield which is caused by the dicing step. A dicing step is generally performed while pure water whose specific resistance is decreased by dissolution of a carbonic acid gas or the like is supplied to a cut portion, in order to cool down a substrate, remove swarf, and prevent electrification, for example. Providing a conductive layer or a semiconductor layer in the separation regions 713 allows a reduction in the usage of the pure water. Therefore, the cost of manufacturing semiconductor devices can be reduced. Thus, semiconductor devices can be manufactured with improved productivity.

<Electronic Component>

In this embodiment, examples in which the chip 715 is used in an electronic component will be described with reference to FIGS. 40A and 40B. Note that the electronic component is also referred to as a semiconductor package or an IC package. The electronic component has a plurality of standards and names depending on a terminal extraction direction and a terminal shape.

The electronic component is completed when the semiconductor device described in any of the above embodiments is combined with components other than the semiconductor device in an assembly process (post-process).

The post-process will be described with reference to a flow chart in FIG. 40A. After the semiconductor device of one embodiment of the present invention and the like are provided over the substrate 711 in a pre-process, a back surface grinding step in which a back surface (a surface where the semiconductor device and the like are not formed) of the substrate 711 is ground is performed (Step S721). When the substrate 711 is thinned by grinding, the size of the electronic component can be reduced.

Next, the substrate 711 is divided into a plurality of chips 715 in a dicing step (Step S722). Then, the divided chips 715 are individually bonded to a lead frame in a die bonding step (Step S723). To bond a chip and a lead frame in the die bonding step, a method such as resin bonding or tape-automated bonding is selected as appropriate depending on products. Note that the chip may be bonded to an interposer substrate instead of the lead frame.

Next, a wire bonding step for electrically connecting a lead of the lead frame and an electrode on the chip through a metal wire is performed (Step S724). As the metal wire, a silver wire or a gold wire can be used. Ball bonding or wedge bonding can be used as the wire bonding.

The wire-bonded chip is subjected to a molding step of sealing the chip with an epoxy resin or the like (Step S725). Through the molding step, the inside of the electronic component is filled with a resin, so that a circuit portion incorporated in the chip and a wire for connecting the chip to the lead can be protected from external mechanical force, and deterioration of characteristics (decrease in reliability) due to moisture or dust can be reduced.

Subsequently, the lead of the lead frame is plated in a lead plating step (Step S726). This plating process prevents rust of the lead and facilitates soldering at the time of mounting the chip on a printed wiring board in a later step. Then, the lead is cut and processed in a formation step (Step S727).

Next, a printing (marking) step is performed on a surface of the package (Step S728). After a testing step (Step S729) for checking whether an external shape is good and whether there is malfunction, for example, the electronic component is completed.

FIG. 40B is a perspective schematic diagram of a completed electronic component. FIG. 40B is a perspective schematic diagram illustrating a quad flat package (QFP) as an example of the electronic component. An electronic component 750 in FIG. 40B includes a lead 755 and the chip 715. The electronic component 750 may include more than one chip 715.

The electronic component 750 in FIG. 40B is mounted on a printed circuit board 752, for example. A plurality of electronic components 750 that are combined and electrically connected to each other over the printed circuit board 752; thus, a circuit board on which the electronic components are mounted (a circuit board 754) is completed. The completed circuit board 754 is provided in an electronic device or the like.

<Display Device>

Next, an example of a display device including any of the above-described transistors and/or semiconductor devices will be described. FIG. 41A is a block diagram illustrating a structure example of a display device 500.

The display device 500 in FIG. 41A includes driver circuits 511, 521 a, and 521 b, and a display region 531. Note that the driver circuits 511, 521 a, and 521 b are collectively referred to as a driver circuit or a peripheral driver circuit in some cases.

The driver circuits 521 a and 521 b can function as, for example, scan line driver circuits. The driver circuit 511 can function as, for example, a signal line driver circuit. Note that one of the driver circuits 521 a and 521 b may be omitted. Alternatively, some sort of circuit facing the driver circuit 511 with the display region 531 provided therebetween may be provided.

The display device 500 illustrated as an example in FIG. 41A includes p wirings 535 which are arranged substantially parallel to each other and whose potentials are controlled by the driver circuit 521 a and/or the driver circuit 521 b, and q wirings 536 which are arranged substantially parallel to each other and whose potentials are controlled by the driver circuit 511. The display region 531 includes a plurality of pixels 532 arranged in a matrix. The pixel 532 includes a pixel circuit 534 and a display element.

When every three pixels 532 function as one pixel, full-color display can be provided. The three pixels 532 control the transmittance, reflectance, amount of emitted light, or the like of red light, green light, or blue light. The light colors controlled by the three pixels 532 are not limited to the combination of red, green, and blue, and may be yellow, cyan, and magenta.

A pixel 532 that controls white light may be added to the pixels that control red light, green light, and blue light so that the four pixels 532 will collectively serve as one pixel. The addition of the pixel 532 that controls white light can heighten the luminance of the display region. When the number of the pixels 532 functioning as one pixel is increased to use red, green, blue, yellow, cyan, and magenta in appropriate combination, the range of color reproduction can be widened.

For example, using the pixels arranged in a 1920×1080 matrix, the display device 500 can be obtained which can display an image with “full high definition” (also referred to as “2K resolution”, “2K1K”, “2K”, and the like). Using the pixels arranged in a 3840×2160 matrix, the display device 500 can be obtained which can display an image with “ultra-high definition” (also referred to as “4K resolution”, “4K2K”, “4K”, and the like). Using the pixels arranged in a 7680×4320 matrix, the display device 500 can be obtained which can display an image with “super high definition” (also referred to as “8K resolution”, “8K4K”, “8K”, and the like). Using a larger number of pixels, the display device 500 can be obtained which can display an image with 16K or 32K resolution.

A wiring 535_g on the g-th row (g is a natural number larger than or equal to 1 and smaller than or equal to p) is electrically connected to q pixels 532 on the g-th row among the plurality of pixels 532 arranged in p rows and q columns (p and q are each a natural number larger than or equal to 1) in the display region 531. A wiring 536_h on the h-th column (h is a natural number larger than or equal to 1 and smaller than or equal to q) is electrically connected to p pixels 532 on the h-th column among the plurality of pixels 532 arranged in p rows and q columns.

[Display Element]

The display device 500 can employ various modes and include various display elements. Examples of the display element include a display element including a display medium whose contrast, luminance, reflectance, transmittance, or the like is changed by electrical or magnetic effect, such as an electroluminescence (EL) element (e.g., an organic EL element, an inorganic EL element, or an EL element including organic and inorganic materials), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a display element using micro electro mechanical systems (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), MIRASOL (registered trademark), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, or a display element using a carbon nanotube. Alternatively, quantum dots may be used as the display element.

Note that examples of display devices using EL elements include an EL display. Examples of display devices including electron emitters are a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of display devices including quantum dots include a quantum dot display. Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display device including electronic ink, electronic liquid powder (registered trademark), or electrophoretic elements include electronic paper. For example, the display device may be a plasma display panel (PDP). The display device may be a retina scanning type projection device.

In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption.

Note that in the case of using an LED, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Providing graphene or graphite in such a manner enables easy formation of a nitride semiconductor film thereover, such as an n-type GaN semiconductor layer including crystals. Furthermore, a p-type GaN semiconductor layer including crystals, or the like, can be provided thereover, and thus the LED can be formed. Note that an AlN layer may be provided between the n-type GaN semiconductor layer including crystals and graphene or graphite. The GaN semiconductor layers included in the LED may be formed by MOCVD. Note that when the graphene is provided, the GaN semiconductor layers included in the LED can also be formed by a sputtering method.

FIGS. 41B and 41C and FIGS. 42A and 42B illustrate circuit structure examples that can be used for the pixel 532.

[Example of Pixel Circuit for Light-Emitting Display Device]

The pixel circuit 534 in FIG. 41B includes transistors 461, 468, and 464, and a capacitor 463. The pixel circuit 534 in FIG. 41B is electrically connected to a light-emitting element 469 that can function as a display element.

The transistors 461, 468, and 464 can be OS transistors. It is particularly preferable to use an OS transistor as the transistor 461.

One of a source electrode and a drain electrode of the transistor 461 is electrically connected to the wiring 536_h. A gate electrode of the transistor 461 is electrically connected to the wiring 535_g. The wiring 536_h supplies a video signal.

The transistor 461 has a function of controlling writing of a video signal to a node 465.

One of a pair of electrodes of the capacitor 463 is electrically connected to the node 465, and the other is electrically connected to a node 467. The other of the source electrode and the drain electrode of the transistor 461 is electrically connected to the node 465.

The capacitor 463 has a function of a storage capacitor for storing data written to the node 465.

One of a source electrode and a drain electrode of the transistor 468 is electrically connected to a potential supply line VL_a, and the other of the source electrode and the drain electrode of the transistor 468 is electrically connected to the node 467. A gate electrode of the transistor 468 is electrically connected to the node 465.

One of a source electrode and a drain electrode of the transistor 464 is electrically connected to a potential supply line V0, and the other of the source electrode and the drain electrode of the transistor 464 is electrically connected to the node 467. A gate electrode of the transistor 464 is electrically connected to the wiring 535_g.

One of an anode and a cathode of the light-emitting element 469 is electrically connected to a potential supply line VL_b, and the other is electrically connected to the node 467.

As the light-emitting element 469, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used, for example. Note that the light-emitting element 469 is not limited thereto and may be an inorganic EL element containing an inorganic material, for example.

A high power supply potential V_(DD) is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential V_(SS) is supplied to the other, for example.

In the display device 500 including the pixel circuits 534 in FIG. 41B, the pixels 532 are sequentially selected row by row by the driver circuit 521 a and/or the driver circuit 521 b, so that the transistors 461 and 464 are turned on and a video signal is written to the node 465.

The pixel 532 in which the data has been written to the node 465 is brought into a holding state when the transistors 461 and 464 are turned off. The amount of current flowing between the source electrode and the drain electrode of the transistor 468 is controlled in accordance with the potential of the data written to the node 465. The light-emitting element 469 emits light with a luminance corresponding to the amount of flowing current. This operation is sequentially performed row by row; thus, an image can be displayed.

As shown in FIG. 42A, the transistors 461, 464, and 468 may be transistors with back gates. In each of the transistors 461 and 464 in FIG. 42A, the gate is electrically connected to the back gate. Thus, the gate and the back gate always have the same potential. The back gate of the transistor 468 is electrically connected to the node 467. Therefore, the back gate always has the same potential as the node 467.

As at least one of the transistors 461, 468, and 464, the transistor 100 or 200 described above can be used.

[Example of Pixel Circuit for Liquid Crystal Display Device]

The pixel circuit 534 in FIG. 41C includes the transistor 461 and the capacitor 463. The pixel circuit 534 in FIG. 41C is electrically connected to a liquid crystal element 462 that can function as a display element. It is preferable to use an OS transistor as the transistor 461.

The potential of one of a pair of electrodes of the liquid crystal element 462 is set as appropriate according to the specifications of the pixel circuit 534. For example, one of the pair of electrodes of the liquid crystal element 462 may be supplied with a common potential, or may have the same potential as a capacitor line CL. Further, the potential applied to one of the pair of electrodes of the liquid crystal element 462 may be different among the pixels 532. The other of the pair of electrodes of the liquid crystal element 462 is electrically connected to a node 466. The alignment state of the liquid crystal element 462 depends on data written to the node 466.

As a driving method of the display device including the liquid crystal element 462, any of the following modes can be used, for example: a twisted nematic (TN) mode, a super-twisted nematic (STN) mode, a vertical alignment (VA) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, a transverse bend alignment (TBA) mode, and the like. Other examples of the driving method of the display device include an electrically controlled birefringence (ECB) mode, a polymer dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, and a guest-host mode. Note that one embodiment of the present invention is not limited thereto, and various liquid crystal elements and driving methods can be used.

In the case where a liquid crystal element is used as the display element, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like, depending on conditions.

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while the temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5 wt. % or more of a chiral material is mixed is used for a liquid crystal layer in order to improve the temperature range. The liquid crystal composition that includes the liquid crystal exhibiting a blue phase and a chiral material has a short response time of 1 msec or less, and has optical isotropy, which makes the alignment process unnecessary and the viewing angle dependence small. An alignment film does not need to be provided and rubbing treatment is thus not necessary; accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Thus, productivity of the liquid crystal display device can be improved.

Furthermore, it is possible to use a method called domain multiplication or multi-domain design, in which a pixel is divided into some regions (subpixels) and molecules are aligned in different directions in their respective regions.

The specific resistivity of the liquid crystal material is greater than or equal to 1×10⁹ Ω·cm, preferably greater than or equal to 1×10¹¹ Ω·cm, more preferably greater than or equal to 1×10¹² Ω·cm. Note that the specific resistivity in this specification is measured at 20° C.

In the pixel circuit 534 on the g-th row and the h-th column, one of the source electrode and the drain electrode of the transistor 461 is electrically connected to the wiring 536_h, and the other of the source electrode and the drain electrode of the transistor 461 is electrically connected to the node 466. The gate electrode of the transistor 461 is electrically connected to the wiring 535_g. The wiring 536_h supplies a video signal. The transistor 461 has a function of controlling writing of a video signal to the node 466.

One of a pair of electrodes of the capacitor 463 is electrically connected to a wiring to which a particular potential is supplied (hereinafter referred to as a capacitor line CL), and the other is electrically connected to the node 466. The potential of the capacitor line CL is set in accordance with the specifications of the pixel circuit 534 as appropriate. The capacitor 463 has a function of a storage capacitor for storing data written to the node 466.

For example, in the display device 500 including the pixel circuit 534 in FIG. 41C, the pixel circuits 534 are sequentially selected row by row by the driver circuit 521 a and/or the driver circuit 521 b, so that the transistors 461 are turned on and a video signal is written to the node 466.

The pixel circuit 534 in which the video signal has been written to the node 466 is brought into a holding state when the transistor 461 is turned off. This operation is sequentially performed row by row; thus, an image can be displayed on the display region 531.

As shown in FIG. 42B, the transistor 461 may be a transistor with a back gate. In the transistor 461 in FIG. 42B, the gate is electrically connected to the back gate. Thus, the gate and the back gate always have the same potential.

[Structure Example of Peripheral Circuit]

FIG. 43A shows a structure example of the driver circuit 511. The driver circuit 511 includes a shift register 512, a latch circuit 513, and a buffer 514. FIG. 43B shows a structure example of the driver circuit 521 a. The driver circuit 521 a includes a shift register 522 and a buffer 523. The structure of the driver circuit 521 b can be similar to that of the driver circuit 521 a.

A start pulse SP, a clock signal CLK, and the like are input to the shift register 512 and the shift register 522.

[Structure Example of Display Device]

With use of any of the transistors described in the above embodiments, some or all of driver circuits which include shift registers can be formed over a substrate where a pixel portion is formed, whereby a system-on-panel can be obtained.

A structure example of a display device including a liquid crystal element and a structure example of a display device including an EL element will be described in this embodiment. In FIG. 44A, a sealant 4005 is provided so as to surround a pixel portion 4002 provided over a first substrate 4001. The pixel portion 4002 is sealed with the first substrate 4001, the sealant 4005, and a second substrate 4006. In FIG. 44A, a signal line driver circuit 4003 and a scan line driver circuit 4004 each are formed using a single-crystal semiconductor or a polycrystalline semiconductor over a substrate prepared separately, and mounted in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. Further, various signals and potentials are supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, and the pixel portion 4002 from flexible printed circuits (FPCs) 4018 a and 4018 b.

In FIGS. 44B and 44C, the sealant 4005 is provided so as to surround the pixel portion 4002 and the scan line driver circuit 4004 which are provided over the first substrate 4001. Furthermore, the second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Thus, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with display elements with the use of the first substrate 4001, the sealant 4005, and the second substrate 4006. In FIGS. 44B and 44C, a signal line driver circuit 4003 formed using a single crystal semiconductor or a polycrystalline semiconductor over a substrate separately prepared is mounted in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. In FIGS. 44B and 44C, various signals and potentials are supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, and the pixel portion 4002 from an FPC 4018.

Although FIGS. 44B and 44C each illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001, this structure is not necessarily employed. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

Note that a connection method of a separately formed driver circuit is not particularly limited, and wire bonding, a chip on glass (COG), a tape carrier package (TCP), a chip on film (COF), or the like can be used. FIG. 44A illustrates an example in which the signal line driver circuit 4003 and the scan line driver circuit 4004 are mounted by COG. FIG. 44B illustrates an example in which the signal line driver circuit 4003 is mounted by a COG method. FIG. 44C illustrates an example in which the signal line driver circuit 4003 is mounted by TCP.

In some cases, the display device encompasses a panel in which a display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.

The pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors and any of the transistors which are described in the above embodiments can be used.

FIGS. 45A and 45B correspond to cross-sectional views taken along chain line N1-N2 in FIG. 44B. As shown in FIGS. 45A and 45B, the display device has an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019. The electrode 4015 is electrically connected to a wiring 4014 in an opening formed in insulating layers 4110 to 4112.

The electrode 4015 is formed using the same conductive layer as a first electrode layer 4030, and the wiring 4014 is formed using the same conductive layer as source and drain electrodes of transistors 4010 and 4011.

Each of the pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 includes a plurality of transistors. In FIGS. 45A and 45B, the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scan line driver circuit 4004 are shown as an example. The insulating layers 4112, 4111, and 4110 are provided over the transistors 4010 and 4011 in FIG. 45A, and a bank 4510 is further provided over the insulating layer 4112 in FIG. 45B.

The transistors 4010 and 4011 are provided over an insulating layer 4102. The transistors 4010 and 4011 each include an electrode 4017 over the insulating layer 4102. An insulating layer 4103 is formed over the electrode 4017. The electrode 4017 can serve as a back gate electrode.

Any of the transistors described in the above embodiments can be used as the transistors 4010 and 4011. As the transistors 4010 and 4011, OS transistors may be used. A change in the electrical characteristics of OS transistors is suppressed and thus the OS transistors are electrically stable. Accordingly, the display devices of this embodiment illustrated in FIGS. 45A and 45B can be highly reliable display devices.

In the OS transistor, the current in an off state (the off-state current) can be small. Accordingly, an electrical signal such as an image signal can be held for a longer period, and a writing interval can be set longer in an on state. Accordingly, the frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption.

In the OS transistor, relatively high field-effect mobility can be obtained, whereby high-speed operation is possible. Consequently, when the above transistor is used in a driver circuit portion or a pixel portion of a display device, high-quality images can be obtained. Since the driver circuit portion and the pixel portion can be formed over one substrate with use of the above transistor, the number of components of the display device can be reduced.

The display devices illustrated in FIGS. 45A and 45B each include a capacitor 4020. The capacitor 4020 includes an electrode formed through the same steps as the gate electrode of the transistor 4010 and an electrode formed through the same steps as the back gate electrode of the transistor 4010. The electrodes overlap with each other with the insulating layer 4103 provided therebetween.

In general, the capacitance of a capacitor provided in a pixel portion of a display device is set in consideration of leakage current or the like of transistors provided in a pixel portion so that charges can be held for a predetermined period. The capacitance of the capacitor can be set considering off-state current of the transistor, or the like.

For example, when an OS transistor is used in a pixel portion of a liquid crystal display device, the capacitance of the capacitor can be one-third or less, or one-fifth or less, of the capacitance of liquid crystal. Using an OS transistor can omit the formation of a capacitor.

The transistor 4010 included in the pixel portion 4002 is electrically connected to the display element. An example of a liquid crystal display device using a liquid crystal element as a display element is illustrated in FIG. 45A. In FIG. 45A, a liquid crystal element 4013 that is the display element includes the first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 functioning as alignment films are provided so that the liquid crystal layer 4008 is provided therebetween. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 positioned therebetween.

A spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer and is provided in order to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Alternatively, a spherical spacer may be used.

In the display device, a black matrix (a light-blocking layer), an optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, and the like may be provided as appropriate. For example, circular polarization may be employed by using a polarizing substrate and a retardation substrate. In addition, a backlight, a sidelight, or the like may be used as a light source.

As the display element included in the display device, a light-emitting element utilizing electroluminescence (also referred to as an “EL element”) can be used. An EL element includes a layer containing a light-emitting compound (also referred to as an “EL layer”) between a pair of electrodes. By generating a potential difference between the pair of electrodes that is greater than the threshold voltage of the EL element, holes are injected to the EL layer from the anode side and electrons are injected to the EL layer from the cathode side. The injected electrons and holes are recombined in the EL layer, so that a light-emitting substance contained in the EL layer emits light.

EL elements are classified depending on whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by voltage application, electrons are injected from one electrode to the EL layer and holes are injected from the other electrode to the EL layer. The carriers (electrons and holes) are recombined; thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Based on such a mechanism, such a light-emitting element is referred to as a current-excitation type light-emitting element.

In addition to the light-emitting compound, the EL layer may further include any of a substance with an excellent hole-injection property, a substance with an excellent hole-transport property, a hole-blocking material, a substance with an excellent electron-transport property, a substance with an excellent electron-injection property, a substance with a bipolar property (a substance with an excellent electron-transport property and an excellent hole-transport property), and the like.

The EL layer can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element according to their element structures. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is given here using an organic EL element as a light-emitting element.

In order to extract light emitted from the light-emitting element, it is acceptable as long as at least one of a pair of electrodes is transparent. The transistor and the light-emitting element are formed over a substrate. The light-emitting element can have a top emission structure in which light emission is extracted from the side opposite to the substrate; a bottom emission structure in which light emission is extracted from the substrate side; or a dual emission structure in which light emission is extracted from both the side opposite to the substrate and the substrate side.

FIG. 45B illustrates an example of a light-emitting display device (also referred to as an “EL display device”) using a light-emitting element as a display element. A light-emitting element 4513 as the display element is electrically connected to the transistor 4010 provided in the pixel portion 4002. The structure of the light-emitting element 4513 is the layered structure including the first electrode layer 4030, a light-emitting layer 4511, and the second electrode layer 4031; however, this embodiment is not limited to this structure. The structure of the light-emitting element 4513 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4513, or the like.

The bank 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable that the bank 4510 be formed using a photosensitive resin material in such a manner that an opening is formed over the first electrode layer 4030 so that a side surface of the opening slopes with continuous curvature.

The light-emitting layer 4511 may be formed using a single layer or a plurality of layers stacked.

A protective layer may be formed over the second electrode layer 4031 and the bank 4510 in order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element 4513. For the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, diamond like carbon (DLC), or the like can be used. In addition, in a space which is enclosed by the first substrate 4001, the second substrate 4006, and the sealant 4005, a filler 4514 is provided for sealing. It is preferable that, in this manner, the display device be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover member with high air-tightness and little degasification so that the display device is not exposed to the outside air.

As the filler 4514, an ultraviolet curable resin or a thermosetting resin can be used as well as an inert gas such as nitrogen or argon; for example, polyvinyl chloride (PVC), an acrylic-based resin, polyimide, an epoxy-based resin, a silicone-based resin, polyvinyl butyral (PVB), ethylene vinyl acetate (EVA), or the like can be used. A drying agent may be contained in the filler 4514.

A glass material such as a glass frit, or a resin that is curable at room temperature, such as a two-component-mixture-type resin, a light curable resin, and a thermosetting resin can be used for the sealant 4005. A drying agent may be contained in the sealant 4005.

In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.

When the light-emitting element has a microcavity structure, light with high color purity can be extracted. Furthermore, when a microcavity structure and a color filter are used in combination, the glare can be reduced and visibility of a display image can be increased.

The first electrode layer and the second electrode layer (also called a pixel electrode layer, a common electrode layer, a counter electrode layer, or the like) for applying voltage to the display element may have light-transmitting properties or light-reflecting properties, which depends on the direction in which light is extracted, the position where the electrode layer is provided, and the pattern structure of the electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The first electrode layer 4030 and the second electrode layer 4031 each can also be formed using one or more kinds selected from metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag); an alloy thereof or a nitride thereof.

A conductive composition containing a conductive high molecular compound (also called conductive polymer) can be used for the first electrode layer 4030 and the second electrode layer 4031. As the conductive high molecular compound, a so-called π-electron conjugated conductive high molecular compound can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

Since the transistor is easily broken due to static electricity or the like, a protection circuit for protecting the driver circuit is preferably provided. The protection circuit is preferably formed using a nonlinear element.

With use of the shift registers described in the above embodiment, a highly reliable display device can be provided. With use of any of the transistors described in the above embodiments, a highly reliable display device can be provided. With use of any of the transistors described in the above embodiments, a display device that has a high resolution, a large size, and high display quality can be provided. Furthermore, a display device with low power consumption can be provided.

<Display Module>

A display module is described as an example of a semiconductor device using any of the above-described transistors. In a display module 6000 in FIG. 46, a touch sensor 6004 connected to an FPC 6003, a display panel 6006 connected to an FPC 6005, a backlight unit 6007, a frame 6009, a printed circuit board 6010, and a battery 6011 are provided between an upper cover 6001 and a lower cover 6002. Note that the backlight unit 6007, the battery 6011, the touch sensor 6004, and the like are not provided in some cases.

The semiconductor device of one embodiment of the present invention can be used for, for example, the touch sensor 6004, the display panel 6006, an integrated circuit mounted on the printed circuit board 6010, and the like. For example, the above-described display device can be used in the display panel 6006.

The shapes and sizes of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch sensor 6004, the display panel 6006, and the like.

The touch sensor 6004 can be a resistive touch sensor or a capacitive touch sensor and may be formed to overlap with the display panel 6006. The display panel 6006 can have a touch sensor function. For example, an electrode for a touch sensor may be provided in each pixel of the display panel 6006 so that a capacitive touch panel function is added. Alternatively, a photosensor may be provided in each pixel of the display panel 6006 so that an optical touch sensor function is added. In the case where the touch sensor 6004 is not necessarily provided, the touch sensor 6004 can be omitted.

The backlight unit 6007 includes a light source 6008. The light source 6008 may be provided at an end portion of the backlight unit 6007 and a light diffusing plate may be used. When a light-emitting display device or the like is used for the display panel 6006, the backlight unit 6007 can be omitted.

The frame 6009 protects the display panel 6006 and also functions as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010 side. The frame 6009 may function as a radiator plate.

The printed circuit board 6010 is provided with a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, and the like. As a power source for supplying power to the power supply circuit, the battery 6011 or a commercial power source may be used. Note that the battery 6011 can be omitted in the case where a commercial power source is used as the power source.

The display module 6000 can be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments, Example, and the like.

Embodiment 4

A semiconductor device of one embodiment of the present invention can be used for a variety of electronic devices. FIG. 47 illustrates specific examples of electronic devices including the semiconductor device of one embodiment of the present invention.

Examples of electronic devices each utilizing the semiconductor device of one embodiment of the present invention are as follows: display devices of televisions, monitors, and the like, lighting devices, desktop personal computers and laptop personal computers, word processors, image reproduction devices which reproduce still images and moving images stored in recording media such as digital versatile discs (DVDs), portable CD players, portable radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless phone handsets, transceivers, portable wireless devices, mobile phones, car phones, portable game machines, tablet terminals, large-sized game machines such as pachinko machines, calculators, portable information terminals, electronic notebooks, e-book readers, electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, high-frequency heating appliances such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air-conditioning systems such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for preserving DNA, flashlights, tools such as a chain saw, smoke detectors, and medical equipment such as dialyzers. Furthermore, industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for leveling the amount of power supply and smart grid can be given.

In addition, moving objects driven by electric motors using electric power from the power storage devices are also included in the category of electronic devices. Examples of the moving objects are electric vehicles (EV), hybrid electric vehicles (HEV) which include both an internal-combustion engine and a motor, plug-in hybrid electric vehicles (PHEV), tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles, motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats, ships, submarines, helicopters, aircrafts, rockets, artificial satellites, space probes, planetary probes, and spacecrafts.

FIG. 47 illustrates examples of electronic devices. In FIG. 47, a display device 8000 is an example of an electronic device including a semiconductor device 8004 of one embodiment of the present invention. Specifically, the display device 8000 corresponds to a display device for TV broadcast reception and includes a housing 8001, a display portion 8002, speaker portions 8003, the semiconductor device 8004, and a power storage device 8005. The semiconductor device 8004 of one embodiment of the present invention is provided in the housing 8001. The semiconductor device 8004 can hold control data, a control program, or the like. The display device 8000 can receive electric power from a commercial power supply. Alternatively, the display device 8000 can use electric power stored in the power storage device 8005.

A display device such as a liquid crystal display device, a light-emitting display device in which a light-emitting element such as an organic EL element is provided in each pixel, an electrophoresis display device, a digital micromirror device (DMD), a plasma display panel (PDP), or a field emission display (FED) can be used for the display portion 8002.

Note that the display device includes, in its category, all of information display devices for personal computers, advertisement displays, and the like besides TV broadcast reception.

In FIG. 47, an installation lighting device 8100 is an example of an electronic device including a semiconductor device 8103 of one embodiment of the present invention. Specifically, the lighting device 8100 includes a housing 8101, a light source 8102, the semiconductor device 8103, a power storage device 8105, and the like. Although FIG. 47 illustrates the case where the semiconductor device 8103 is provided in a ceiling 8104 on which the housing 8101 and the light source 8102 are installed, the semiconductor device 8103 may be provided in the housing 8101. The semiconductor device 8103 can hold data such as emission luminance of the light source 8102, a control program, or the like. The lighting device 8100 can receive electric power from a commercial power supply. Alternatively, the lighting device 8100 can use electric power stored in the power storage device.

Note that although the installation lighting device 8100 provided in the ceiling 8104 is illustrated in FIG. 47 as an example, the semiconductor device of one embodiment of the present invention can be used in an installation lighting device provided in, for example, a wall 8405, a floor 8406, a window 8407, or the like other than the ceiling 8104. Alternatively, the semiconductor device of one embodiment of the present invention can be used in a tabletop lighting device or the like.

As the light source 8102, an artificial light source which emits light artificially by using electric power can be used. Specifically, an incandescent lamp, a discharge lamp such as a fluorescent lamp, and light-emitting elements such as an LED and an organic EL element are given as examples of the artificial light source.

In FIG. 47, an air conditioner including an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device including a semiconductor device 8203 of one embodiment of the present invention. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, the semiconductor device 8203, and a power storage device 8205. Although FIG. 47 illustrates the case where the semiconductor device 8203 is provided in the indoor unit 8200, the semiconductor device 8203 may be provided in the outdoor unit 8204. Alternatively, the semiconductor devices 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The semiconductor device 8203 can hold control data of the air conditioner, a control program, or the like. The air conditioner can receive electric power from a commercial power supply. Alternatively, the air conditioner can use electric power stored in the power storage device 8205.

Note that although the split-type air conditioner including the indoor unit and the outdoor unit is illustrated in FIG. 47 as an example, the semiconductor device of one embodiment of the present invention can be used in an air conditioner in which the functions of an indoor unit and an outdoor unit are integrated in one housing.

In FIG. 47, an electric refrigerator-freezer 8300 is an example of an electronic device including a semiconductor device 8304 of one embodiment of the present invention. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a door for a refrigerator 8302, a door for a freezer 8303, the semiconductor device 8304, a power storage device 8305, and the like. In FIG. 47, the power storage device 8305 is provided in the housing 8301. The semiconductor device 8304 can hold control data of the electric refrigerator-freezer 8300, a control program, or the like. The electric refrigerator-freezer 8300 can receive electric power from a commercial power supply. Alternatively, the electric refrigerator-freezer 8300 can use electric power stored in the power storage device 8305.

An information terminal 2910 illustrated in FIG. 48A includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. A display panel and a touch screen that use a flexible substrate are provided in the display portion 2912. In the housing 2911 of the information terminal 2910, an antenna, a battery, and the like are provided. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, or an e-book reader.

A notebook personal computer 2920 illustrated in FIG. 48B includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. In the housing 2921 of the notebook personal computer 2920, an antenna, a battery, and the like are provided.

A video camera 2940 illustrated in FIG. 48C includes a housing 2941, a housing 2942, a display portion 2943, operation switches 2944, a lens 2945, a joint 2946, and the like. The operation switches 2944 and the lens 2945 are provided for the housing 2941, and the display portion 2943 is provided for the housing 2942. In the housing 2941 of the video camera 2940, an antenna, a battery, and the like are provided. The housing 2941 and the housing 2942 are connected to each other with the joint 2946, and the angle between the housing 2941 and the housing 2942 can be changed with the joint 2946. The orientation of an image on the display portion 2943 may be changed and display and non-display of an image can be switched depending on the angle between the housings 2941 and 2942.

FIG. 48D illustrates an example of a bangle-type information terminal. An information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In the housing 2951 of the information terminal 2950, an antenna, a battery, and the like are provided. The display portion 2952 is supported by the housing 2951 having a curved surface. A display panel formed with a flexible substrate is provided in the display portion 2952, whereby the information terminal 2950 can be a user-friendly information terminal that is flexible and lightweight.

FIG. 48E illustrates an example of a watch-type information terminal. An information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input output terminal 2966, and the like. In the housing 2961 of the information terminal 2960, an antenna, a battery, and the like are provided. The information terminal 2960 is capable of executing a variety of applications such as mobile phone calls, e-mailing, viewing and editing texts, music reproduction, Internet communication, and a computer game.

The display surface of the display portion 2962 is curved, and images can be displayed on the curved display surface. In addition, the display portion 2962 includes a touch sensor, and operation can be performed by touching the screen with a finger, a stylus, or the like. For example, by touching an icon 2967 displayed on the display portion 2962, application can be started. With the operation switch 2965, a variety of functions such as time setting, power on/off, on/off of wireless communication, setting and cancellation of a silent mode, and setting and cancellation of a power saving mode can be performed. For example, the functions of the operation switch 2965 can be set by setting the operation system incorporated in the information terminal 2960.

The information terminal 2960 can employ near field communication that is a communication method based on an existing communication standard. In that case, for example, mutual communication between the information terminal 2960 and a headset capable of wireless communication can be performed, and thus hands-free calling is possible. Moreover, the information terminal 2960 includes the input output terminal 2966, and data can be directly transmitted to and received from another information terminal via a connector. In addition, charging via the input output terminal 2966 is possible. Note that the charging operation may be performed by wireless power feeding without using the input output terminal 2966.

FIG. 48F is an external view illustrating an example of a car. A car 2980 includes a car body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The car 2980 also includes an antenna, a battery, and the like.

A memory device including the semiconductor device of one embodiment of the present invention can hold control data, a control program, or the like of the above electronic device for a long time. With the use of the semiconductor device of one embodiment of the present invention, a highly reliable electronic device can be provided.

This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments, Example, and the like.

Embodiment 5

In this embodiment, the structure of an oxide semiconductor will be described. Oxide semiconductors are classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

From another perspective, oxide semiconductors are classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and not have fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.

This means that a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. In contrast, an a-like OS, which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS is close to an amorphous oxide semiconductor in terms of physical properties.

<CAAC-OS>

First, a CAAC-OS will be described.

A CAAC-OS is an oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

Analysis of a CAAC-OS by X-ray diffraction (XRD) will be described. For example, when the structure of a CAAC-OS including an InGaZnO₄ crystal that is classified as the space group R-3m is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 51A. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in the direction substantially perpendicular to a surface over which the CAAC-OS film is formed (also referred to as a formation surface) or the top surface of the CAAC-OS film. Note that a peak sometimes appears at a 2θ of around 36° in addition to the peak at a 2θ of around 31°. The peak at a 2θ of around 36° is derived from a crystal structure that is classified into the space group Fd-3m; thus, this peak is preferably not exhibited in a CAAC-OS.

On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in the direction parallel to the formation surface, a peak appears at a 2θ of around 56°. This peak is attributed to the (110) plane of the InGaZnO₄ crystal. When analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector to the sample surface as an axis (φ axis), a peak is not clearly observed as shown in FIG. 51B. In contrast, in the case where single crystal InGaZnO₄ is subjected to φ scan with 2θ fixed at around 56°, six peaks which are derived from crystal planes equivalent to the (110) plane are observed as shown in FIG. 51C. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO₄ crystal in the direction parallel to the formation surface of the CAAC-OS, such a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) as is shown in FIG. 51D can be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO₄ crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in the direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 51E shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in the direction perpendicular to the sample surface. As shown in FIG. 51E, a ring-like diffraction pattern is observed. Thus, the electron diffraction using an electron beam with a probe diameter of 300 nm also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in FIG. 51E is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal. The second ring in FIG. 51E is considered to be derived from the (110) plane and the like.

In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, even in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.

FIG. 52A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from the direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 52A shows pellets in which metal atoms are arranged in a layered manner. FIG. 52A proves that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). A pellet reflects unevenness of a formation surface or a top surface of the CAAC-OS, and is parallel to the formation surface or the top surface of the CAAC-OS.

FIGS. 52B and 52C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. FIGS. 52D and 52E are images obtained through image processing of FIGS. 52B and 52C. The method of image processing is as follows. The image in FIG. 52B is subjected to fast Fourier transform (FFT), so that an FFT image is obtained. Then, mask processing is performed such that a range of from 2.8 nm⁻¹ to 5.0 nm⁻¹ from the origin in the obtained FFT image remains. After the mask processing, the FFT image is processed by inverse fast Fourier transform (IFFT) to obtain a processed image. The image obtained in this manner is called an FFT filtering image. The FFT filtering image is a Cs-corrected high-resolution TEM image from which a periodic component is extracted, and shows a lattice arrangement.

In FIG. 52D, a portion where a lattice arrangement is broken is shown by dashed lines. A region surrounded by dashed lines is one pellet. The portion denoted by the dashed lines is a junction of pellets. The dashed lines draw a hexagon, which means that the pellet has a hexagonal shape. Note that the shape of the pellet is not always a regular hexagon but is a non-regular hexagon in many cases.

In FIG. 52E, a dotted line denotes a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement, and a dashed line denotes the change in the direction of the lattice arrangement. A clear crystal grain boundary cannot be observed even in the vicinity of the dotted line. When a lattice point in the vicinity of the dotted line is regarded as a center and surrounding lattice points are joined, a distorted hexagon, pentagon, and/or heptagon can be formed, for example. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in the a-b plane direction, an interatomic bond distance changed by substitution of a metal element, and the like.

As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in the a-b plane direction, and the crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal.

The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has negligible amounts of impurities and defects (e.g., oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

<nc-OS>

Next, an nc-OS will be described.

Analysis of an nc-OS by XRD will be described. When the structure of an nc-OS is analyzed by an out-of-plane method, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.

For example, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of thinned nc-OS including an InGaZnO₄ crystal in the direction parallel to the formation surface, a ring-shaped diffraction pattern (a nanobeam electron diffraction pattern) shown in FIG. 53A is observed. FIG. 53B shows a diffraction pattern obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. As shown in FIG. 53B, a plurality of spots are observed in a ring-like region. In other words, ordering in an nc-OS is not observed with an electron beam with a probe diameter of 50 nm but is observed with an electron beam with a probe diameter of 1 nm.

Furthermore, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape is observed in some cases as shown in FIG. 53C when an electron beam having a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm. This means that an nc-OS has a well-ordered region, i.e., a crystal, in the range of less than 10 nm in thickness. Note that an electron diffraction pattern having regularity is not observed in some regions because crystals are aligned in various directions.

FIG. 53D shows a Cs-corrected high-resolution TEM image of a cross section of an nc-OS observed from the direction substantially parallel to the formation surface. In a high-resolution TEM image, an nc-OS has a region in which a crystal part is observed, such as the part indicated by additional lines in FIG. 53D, and a region in which a crystal part is not clearly observed. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, in particular, greater than or equal to 1 nm and less than or equal to 3 nm. An oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm can be referred to as a microcrystalline oxide semiconductor (fine microcrystalline oxide semiconductor). In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.

As described above, in the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.

Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>

An a-like OS has a structure between those of the nc-OS and the amorphous oxide semiconductor.

FIGS. 54A and 54B are high-resolution cross-sectional TEM images of an a-like OS. FIG. 54A is the high-resolution cross-sectional TEM image of the a-like OS at the start of the electron irradiation. FIG. 54B is the high-resolution cross-sectional TEM image of the a-like OS after the electron (e⁻) irradiation at 4.3×10⁸ e⁻/nm². FIGS. 54A and 54B show that stripe-like bright regions extending vertically are observed in the a-like OS from the start of the electron irradiation. It can also be found that the shape of the bright region changes after the electron irradiation. Note that the bright region is presumably a void or a low-density region.

The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation will be described below.

An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.

Note that it is known that a unit cell of an InGaZnO₄ crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO₄ in the following description. Each of lattice fringes corresponds to the a-b plane of the InGaZnO₄ crystal.

FIG. 55 shows change in the average size of crystal parts (at 22 points to 30 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 55 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose in obtaining TEM images, for example. As shown in FIG. 55, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 1.9 nm at a cumulative electron (e) dose of 4.2×10⁸ e⁻/nm². In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×10⁸ e⁻/nm². As shown in FIG. 55, the average size of crystal parts in an nc-OS and a CAAC-OS are approximately 1.3 nm and approximately 1.8 nm, respectively, regardless of the cumulative electron dose. For observation of electron beam irradiation and TEM, a Hitachi H-9000NAR transmission electron microscope was used. The conditions of electron beam irradiations are as follows: the accelerating voltage is 300 kV; the current density is 6.7×10⁵ e⁻/(nm²·s); and the diameter of irradiation region is 230 nm.

In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with a rhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm³ and lower than 5.9 g/cm³. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that in the case where an oxide semiconductor having a certain composition does not exist in a single crystal structure, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to estimate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be estimated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to estimate the density.

As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stack including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

<Carrier Density of Oxide Semiconductor>

Next, the carrier density of an oxide semiconductor layer will be described below.

Examples of a factor that affects the carrier density of an oxide semiconductor include oxygen vacancies (V_(O)) and impurities in the oxide semiconductor.

As the amount of oxygen vacancies in the oxide semiconductor increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). The density of defect states also increases with an increase in the amount of impurities in the oxide semiconductor. Hence, the carrier density of the oxide semiconductor can be adjusted by controlling the density of defect states in the oxide semiconductor.

An OS transistor will be described. The carrier density of the oxide semiconductor is preferably reduced in order to suppress the negative shift of the threshold voltage of the transistor or reduce the off-state current of the OS transistor. In order to reduce the carrier density of the oxide semiconductor, the impurity concentration in the oxide semiconductor is reduced so that the density of defect states can be reduced. In this specification and the like, the state in which the impurity concentration is low and the density of defect states is low is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic”. The carrier density of a highly purified intrinsic oxide semiconductor is lower than 8×10¹⁵ cm⁻³, preferably lower than 1×10¹¹ cm⁻³, more preferably lower than 1×10¹⁰ cm⁻³ and is higher than or equal to 1×10⁻⁹ cm⁻³.

In contrast, the carrier density of the oxide semiconductor is preferably increased in order to increase the on-state current of the transistor or improve the field-effect mobility of the transistor. In order to increase the carrier density of the oxide semiconductor, it is preferred that the impurity concentration or the density of defect states in the oxide semiconductor be slightly increased, or the bandgap of the oxide semiconductor be narrowed. For example, an oxide semiconductor that has a slightly high impurity concentration or a slightly high density of defect states in the range where a favorable on/off ratio is obtained in the I_(d)-V_(g) characteristics of a transistor can be regarded as substantially intrinsic. Furthermore, an oxide semiconductor that has a high electron affinity and a narrow bandgap and thus has an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that a transistor using an oxide semiconductor with higher electron affinity has a lower threshold voltage.

The oxide semiconductor with an increased carrier density has somewhat n-type conductivity; thus, it can be referred to as a “slightly-n” oxide semiconductor.

The carrier density of a substantially intrinsic oxide semiconductor is preferably higher than or equal to 1×10⁵ cm⁻³ and lower than 1×10¹⁸ cm⁻³, more preferably higher than or equal to 1×10⁷ cm⁻³ and lower than or equal to 1×10¹⁷ cm⁻³, still more preferably higher than or equal to 1×10⁹ cm⁻³ and lower than or equal to 5×10¹⁶ cm⁻³, yet more preferably higher than or equal to 1×10¹⁰ cm⁻³ and lower than or equal to 1×10¹⁶ cm⁻³, and yet still more preferably higher than or equal to 1×10¹¹ cm⁻³ and lower than or equal to 1×10¹⁵ cm⁻³.

The use of the substantially intrinsic oxide semiconductor described above may improve the reliability of the transistor. Here, the reason why the OS transistor has high reliability will be described with reference to FIG. 56. FIG. 56 is an energy band diagram of the OS transistor.

In FIG. 56, GE stands for a gate electrode, GI stands for a gate insulating film, OS stands for an oxide semiconductor, and SD stands for a source electrode or a drain electrode. That is to say, FIG. 56 is an example of the energy band of the gate electrode, the gate insulating film, the oxide semiconductor, and the source electrode or the drain electrode in contact with the oxide semiconductor.

In FIG. 56, a silicon oxide film is used as the gate insulating film, and an In—Ga—Zn oxide is used for the oxide semiconductor. In addition, it is assumed that the transition level (∈_(f)) of a defect that can be formed in the silicon oxide film is located approximately 3.1 eV apart from the conduction band minimum of the gate insulating film, and the Fermi level (E_(f)) of the silicon oxide film at the interface between the oxide semiconductor and the silicon oxide film when the gate voltage (V_(g)) is 30 V is located approximately 3.6 eV apart from the conduction band minimum of the gate insulating film. Note that the Fermi level (E_(f)) of the silicon oxide film varies depending on the gate voltage. For example, as the gate voltage is increased, the Fermi level (E_(f)) of the silicon oxide film at the interface between the oxide semiconductor and the silicon oxide film becomes low. In FIG. 56, hollow circles indicate electrons (carriers), and symbols “X” indicate defect states in the silicon oxide film.

As illustrated in FIG. 56, for example, when the carriers are thermally excited under application of the gate voltage, the carriers are trapped in the defect states (“X” in the diagram), and the charge state of the defect states is changed from positive (“+”) to neutral (“0”). Specifically, in the case where the value obtained by adding the thermal excitation energy to the Fermi level (E_(f)) of the silicon oxide film becomes greater than the transition level (∈_(f)) of the defect, the charge state of the defect states in the silicon oxide film is changed from positive to neutral, and the threshold voltage of the transistor is positively shifted.

When an oxide semiconductor with a different electron affinity is used, the Fermi level of the interface between the gate insulating film and the oxide semiconductor might be changed. When an oxide semiconductor with a greater electron affinity is used, the conduction band minimum of the gate insulating film is relatively high at the interface between the gate insulating film and the oxide semiconductor or in the vicinity of the interface. In that case, the defect states (“X” in FIG. 56) that can be formed in the gate insulating film are also located in a relatively high position; thus, the energy difference between the Fermi level of the gate insulating film and the Fermi level of the oxide semiconductor film is increased. This results in less charge trapped in the gate insulating film. For example, a change in the charge states of the defect states that can be formed in the silicon oxide film is smaller; thus, a change in the threshold voltage of the transistor due to gate bias temperature (GBT) stress can be smaller.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments, Example, and the like.

Embodiment 6

In this embodiment, a deposition apparatus (sputtering apparatus) including a deposition chamber in which a sputtering target can be placed will be described below. The deposition apparatus described in this embodiment can be used as a parallel-plate-type sputtering apparatus, a facing-targets sputtering apparatus, or the like.

Deposition using a facing-targets sputtering apparatus causes less damage to a formation surface and thus facilitates the formation of a film with high crystallinity. For this reason, a facing-targets sputtering apparatus is preferably used for the deposition of a CAAC-OS or the like in some cases.

Note that a deposition method using a parallel-plate-type sputtering apparatus can also be referred to as parallel electrode sputtering (PESP), and a deposition method using a facing-targets sputtering apparatus can also be referred to as vapor deposition sputtering (VDSP).

First, a structure of a deposition apparatus that hardly allows the entry of impurities into a film during deposition or the like will be described with reference to FIG. 57 and FIGS. 58A to 58C.

FIG. 57 is a schematic top view of a single wafer multi-chamber deposition apparatus 2700. The single wafer multi-chamber deposition apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 including a cassette port 2761 for storing substrates and an alignment port 2762 for performing alignment of substrates, an atmosphere-side substrate transfer chamber 2702 through which a substrate is transferred from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703 a where a substrate is carried in and the pressure is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703 b where a substrate is carried out and the pressure is switched from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 where a substrate is transferred in a vacuum, a substrate heating chamber 2705 where a substrate is heated, and deposition chambers 2706 a, 2706 b, and 2706 c in each of which a target is placed for deposition. Note that for the deposition chambers 2706 a, 2706 b, and 2706 c, the structure of a deposition chamber which will be described later can be referred to.

The atmosphere-side substrate transfer chamber 2702 is connected to the load lock chamber 2703 a and the unload lock chamber 2703 b, the load lock chamber 2703 a and the unload lock chamber 2703 b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the substrate heating chamber 2705 and the deposition chambers 2706 a, 2706 b, and 2706 c.

Note that gate valves 2764 are provided in connecting portions between the chambers so that each chamber excluding the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702 can be independently kept in a vacuum state. In each of the atmosphere-side substrate transfer chamber 2702 and the transfer chamber 2704, a transfer robot 2763 is provided, which is capable of transferring substrates.

It is preferable that the substrate heating chamber 2705 also serve as a plasma treatment chamber. In the deposition apparatus 2700, substrates can be transferred without being exposed to the air between treatments, and adsorption of impurities to substrates can be suppressed. In addition, the order of deposition, heat treatment, and the like can be freely determined. Note that the number of transfer chambers, the number of deposition chambers, the number of load lock chambers, the number of unload lock chambers, and the number of substrate heating chambers are not limited to the above, and the number of each of the chambers can be set as appropriate depending on the space for installation or the process conditions.

Next, FIG. 58A, FIG. 58B, and FIG. 58C are a cross-sectional view taken along dashed-dotted line X1-X2, a cross-sectional view taken along dashed-dotted line Y1-Y2, and a cross-sectional view taken along dashed-dotted line Y2-Y3, respectively, in the deposition apparatus 2700 illustrated in FIG. 57.

FIG. 58A illustrates a cross section of the substrate heating chamber 2705 and the transfer chamber 2704, and the substrate heating chamber 2705 includes a plurality of heating stages 2765 which can hold a substrate. Note that the substrate heating chamber 2705 is connected to a vacuum pump 2770 through a valve. As the vacuum pump 2770, a dry pump and a mechanical booster pump can be used, for example.

As a heating mechanism which can be used for the substrate heating chamber 2705, a resistance heater may be used for heating, for example. Alternatively, heat conduction or heat radiation from a medium such as a heated gas may be used as the heating mechanism. For example, rapid thermal annealing (RTA) such as gas rapid thermal annealing (GRTA) or lamp rapid thermal annealing (LRTA) can be used. LRTA is a method for heating an object by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. In GRTA, heat treatment is performed using a high-temperature gas. An inert gas is used as the gas.

Moreover, the substrate heating chamber 2705 is connected to a refiner 2781 through a mass flow controller 2780. Note that although the mass flow controller 2780 and the refiner 2781 can be provided for each of a plurality of kinds of gases, only one mass flow controller 2780 and one refiner 2781 are illustrated for easy understanding. As the gas introduced to the substrate heating chamber 2705, a gas whose dew point is −80° C. or lower, preferably −100° C. or lower can be used; for example, an oxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) are used.

The transfer chamber 2704 includes the transfer robot 2763. The transfer robot 2763 can transfer a substrate to each chamber. Furthermore, the transfer chamber 2704 is connected to the vacuum pump 2770 and a cryopump 2771 through valves. Owing to such a structure, exhaust is performed using the vacuum pump 2770 from the atmospheric pressure to low or medium vacuum (approximately 0.1 Pa to several hundred pascals) and then the valves are switched and exhaust is performed using the cryopump 2771 from the medium vacuum to high or ultra-high vacuum (approximately 0.1 Pa to 1×10⁻⁷ Pa).

Alternatively, two or more cryopumps 2771 may be connected in parallel to the transfer chamber 2704. With such a structure, even when one of the cryopumps is in regeneration, exhaust can be performed using any of the other cryopumps. Note that the above regeneration refers to treatment for discharging molecules (or atoms) entrapped in a cryopump. When molecules (or atoms) are entrapped too much in a cryopump, the exhaust capability of the cryopump is lowered; therefore, regeneration is performed regularly.

FIG. 58B illustrates a cross section of the deposition chamber 2706 b, the transfer chamber 2704, and the load lock chamber 2703 a.

Here, the details of the deposition chamber (sputtering chamber) will be described with reference to FIG. 58B and FIGS. 59A to 59C. FIG. 58A illustrates the inside of the deposition chamber 2706 b. The deposition chamber 2706 b includes a target 2766 a, a target 2766 b, a target shield 2767 a, a target shield 2767 b, a magnet unit 2790 a, a magnet unit 2790 b, a substrate holder 2768, a power source 2791 a, and a power source 2791 b. The target 2766 a is provided on a backing plate 2789 a (not illustrated in FIG. 58B). The target 2766 b is provided on a backing plate 2789 b (not illustrated in FIG. 58B). The power source 2791 a and the power source 2791 b are electrically connected to the target 2766 a and the target 2766 b, respectively. The magnet unit 2790 a is provided on a back side of the target 2766 a with the backing plate 2789 a positioned therebetween. The magnet unit 2790 b is provided on a back side of the target 2766 b with the backing plate 2789 b positioned therebetween. The target shield 2767 a is provided so as to surround an end portion of the target 2766 a and the target shield 2767 b is provided so as to surround an end portion of target 2766 b.

As the power sources 2791 a and 2791 b, an RF power source, a DC power source, an AC power source, or the like can be used. The power sources 2791 a and 2791 b may be different kinds of power sources.

FIGS. 59B and 59C each show potential distribution of the plasma 2788 along dashed-dotted line A-B in FIG. 59A. FIG. 59B shows the potential distribution when a high potential is applied to the backing plate 2789 a and a low potential is applied to the backing plate 2789 b. In that case, a cation is accelerated toward the target 2766 b. FIG. 59C shows the potential distribution when a low potential is applied to the backing plate 2789 a and a high potential is applied to the backing plate 2789 b. In that case, a cation is accelerated toward the target 2766 a. To deposit the oxide semiconductor of one embodiment of the present invention, the state in FIG. 59B and the state in FIG. 59C are alternated.

Note that a substrate 2769 is supported by the substrate holder 2768. The substrate holder 2768 is preferably connected to GND. The substrate holder 2768 may be in a floating state. The substrate holder 2768 is fixed to the deposition chamber 2706 b by a movable member 2784. Owing to the movable member 2784, the substrate holder 2768 can move to a region between the targets 2766 a and 2766 b (a region between targets).

Providing the substrate holder 2768 supporting the substrate 2769 in the region between targets can reduce damage due to plasma in some cases, for example. It is particularly preferable that the substrate holder 2768 and the substrate 2769 be placed in a positive column of the plasma 2788. The positive column of the plasma 2788 is, in each of FIGS. 59B and 59C, a region around the midpoint of A and B where the gradient of the potential distribution is small. When the substrate 2769 is placed in the positive column of the plasma 2788, the substrate 2769 is not exposed to a high electric field portion in the plasma 2788; thus, damage to the plasma 2788 can be reduced.

The substrate holder 2768 and the substrate 2769 may be placed outside the plasma 2788. In that case, the surface of the substrate 2769 is not exposed to a high electric field region of the plasma 2788, leading to a reduction in damage due to the plasma 2788. Note that the utilization efficiencies of the targets 2766 a and 2766 b are decreased as the distance between the plasma 2788 and the substrate 2769 is increased.

The substrate holder 2768 may include a substrate holding mechanism which holds the substrate 2769, a heater which heats the substrate 2769 from the back side, or the like.

The target shields 2767 can suppress deposition of particles sputtered from the target 2766 on a region where deposition is not needed. Moreover, the target shields 2767 are preferably processed to prevent accumulated sputtered particles from being separated. For example, blasting treatment which increases surface roughness may be performed, or roughness may be formed on the surfaces of the target shields 2767.

The deposition chamber 2706 b is connected to the mass flow controller 2780 through a gas heating mechanism 2782, and the gas heating mechanism 2782 is connected to the refiner 2781 through the mass flow controller 2780. With the gas heating mechanism 2782, a gas which is introduced to the deposition chamber 2706 b can be heated to a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. Note that although the gas heating mechanism 2782, the mass flow controller 2780, and the refiner 2781 can be provided for each of a plurality of kinds of gases, only one gas heating mechanism 2782, one mass flow controller 2780, and one refiner 2781 are illustrated for easy understanding. As the gas introduced to the deposition chamber 2706 b, a gas whose dew point is −80° C. or lower, preferably −100° C. or lower can be used; for example, an oxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) are used.

In the case where the refiner is provided near a gas inlet, the length of a pipe between the refiner and the deposition chamber 2706 b is less than or equal to 10 m, preferably less than or equal to 5 m, more preferably less than or equal to 1 m. When the length of the pipe is less than or equal to 10 m, less than or equal to 5 m, or less than or equal to 1 m, the effect of the release of gas from the pipe can be reduced accordingly. As the pipe for the gas, a metal pipe the inside of which is covered with iron fluoride, aluminum oxide, chromium oxide, or the like can be used. With the above pipe, the amount of released gas containing impurities is made small and the entry of impurities into the gas can be reduced as compared with a SUS316L-EP pipe, for example. Furthermore, a high-performance ultra-compact metal gasket joint (UPG joint) may be used as a joint of the pipe. A structure where all the materials of the pipe are metals is preferable because the effect of the generated released gas or the external leakage can be reduced as compared with a structure where a resin or the like is used.

The deposition chamber 2706 b is connected to a turbo molecular pump 2772 and the vacuum pump 2770 through valves.

In addition, the deposition chamber 2706 b is provided with a cryotrap 2751.

The cryotrap 2751 is a mechanism which can adsorb a molecule (or an atom) having a relatively high melting point, such as water. The turbo molecular pump 2772 is capable of stably removing a large-sized molecule (or atom), needs low frequency of maintenance, and thus enables high productivity; on the other hand, it has a low capability in removing hydrogen and water. Hence, the cryotrap 2751 is connected to the deposition chamber 2706 b so as to have a high capability in removing water or the like. The temperature of a refrigerator of the cryotrap 2751 is set to be lower than or equal to 100 K, preferably lower than or equal to 80 K. In the case where the cryotrap 2751 includes a plurality of refrigerators, it is preferable to set the temperatures of the refrigerators at different temperatures because efficient exhaust is possible. For example, the temperature of a first-stage refrigerator may be set to be lower than or equal to 100 K and the temperature of a second-stage refrigerator may be set to be lower than or equal to 20 K. Note that when a titanium sublimation pump is used instead of the cryotrap, a higher vacuum can be achieved in some cases. Using an ion pump instead of a cryopump or a turbo molecular pump can also achieve higher vacuum in some cases.

Note that the exhaust method of the deposition chamber 2706 b is not limited to the above, and a structure similar to that in the exhaust method described above for the transfer chamber 2704 (the exhaust method using the cryopump and the vacuum pump) may be employed. Needless to say, the exhaust method of the transfer chamber 2704 may have a structure similar to that of the deposition chamber 2706 b (the exhaust method using the turbo molecular pump and the vacuum pump).

Note that in each of the transfer chamber 2704, the substrate heating chamber 2705, and the deposition chamber 2706 b which are described above, the back pressure (total pressure) and the partial pressure of each gas molecule (atom) are preferably set as follows. In particular, the back pressure and the partial pressure of each gas molecule (atom) in the deposition chamber 2706 b need to be noted because impurities might enter a film to be formed.

In each of the above chambers, the back pressure (total pressure) is less than or equal to 1×10⁻⁴ Pa, preferably less than or equal to 3×10⁻⁵ Pa, more preferably less than or equal to 1×10⁻⁵ Pa. In each of the above chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is less than or equal to 3×10⁻⁵ Pa, preferably less than or equal to 1×10⁻⁵ Pa, more preferably less than or equal to 3×10⁻⁶ Pa. Moreover, in each of the above chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28 is less than or equal to 3×10⁻⁵ Pa, preferably less than or equal to 1×10⁻⁵ Pa, more preferably less than or equal to 3×10⁻⁶ Pa. Furthermore, in each of the above chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44 is less than or equal to 3×10⁻⁵ Pa, preferably less than or equal to 1×10⁻⁵ Pa, more preferably less than or equal to 3×10⁻⁶ Pa.

Note that a total pressure and a partial pressure in a vacuum chamber can be measured using a mass analyzer. For example, Qulee CGM-051, a quadrupole mass analyzer (also referred to as Q-mass) manufactured by ULVAC, Inc. may be used.

Moreover, the transfer chamber 2704, the substrate heating chamber 2705, and the deposition chamber 2706 b, which are described above, preferably have a small amount of external leakage or internal leakage.

For example, in each of the transfer chamber 2704, the substrate heating chamber 2705, and the deposition chamber 2706 b, which are described above, the leakage rate is less than or equal to 3×10⁻⁶ Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s. The leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is less than or equal to 1×10⁻⁷ Pa·m³/s, preferably less than or equal to 3×10⁻⁸ Pa·m³/s. The leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28 is less than or equal to 1×10⁻⁵ Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s. The leakage rate of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44 is less than or equal to 3×10⁻⁶ Pa·m³/s, preferably less than or equal to 1×10⁻⁶ Pa·m³/s.

Note that a leakage rate can be derived from the total pressure and partial pressure measured using the mass analyzer.

The leakage rate depends on external leakage and internal leakage. The external leakage refers to inflow of gas from the outside of a vacuum system through a minute hole, a sealing defect, or the like. The internal leakage is due to leakage through a partition, such as a valve, in a vacuum system or due to released gas from an internal member. Measures need to be taken from both aspects of external leakage and internal leakage in order that the leakage rate can be set to be less than or equal to the above value.

For example, an open/close portion of the deposition chamber 2706 b can be sealed with a metal gasket. For the metal gasket, metal covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used. The metal gasket achieves higher adhesion than an O-ring, and can reduce the external leakage. Furthermore, with the use of the metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, which is in the passive state, the release of gas containing impurities released from the metal gasket is suppressed, so that the internal leakage can be reduced.

For a member of the deposition apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which releases a smaller amount of gas containing impurities, is used. Alternatively, for the above member, an alloy containing iron, chromium, nickel, and the like covered with the above material may be used. The alloy containing iron, chromium, nickel, and the like is rigid, resistant to heat, and suitable for processing. Here, when surface roughness of the member is decreased by polishing or the like to reduce the surface area, the release of gas can be reduced.

Alternatively, the above member of the deposition apparatus 2700 may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

The member of the deposition apparatus 2700 is preferably formed using only metal when possible. For example, in the case where a viewing window formed with quartz or the like is provided, it is preferable that the surface of the viewing window be thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress release of gas.

When an adsorbed substance is present in the deposition chamber, the adsorbed substance does not affect the pressure in the deposition chamber because it is adsorbed onto an inner wall or the like; however, the adsorbed substance causes gas to be released when the inside of the deposition chamber is evacuated. Therefore, although there is no correlation between the leakage rate and the exhaust rate, it is important that the adsorbed substance present in the deposition chamber be desorbed as much as possible and exhaust be performed in advance with the use of a pump with high exhaust capability. Note that the deposition chamber may be subjected to baking to promote desorption of the adsorbed substance. By the baking, the desorption rate of the adsorbed substance can be increased about tenfold. The baking can be performed at a temperature in the range from 100° C. to 450° C. At this time, when the adsorbed substance is removed while an inert gas is introduced to the deposition chamber, the desorption rate of water or the like, which is difficult to desorb simply by exhaust, can be further increased. Note that when the inert gas which is introduced is heated to substantially the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased. Here, a rare gas is preferably used as an inert gas. Depending on the kind of a film to be deposited, oxygen or the like may be used instead of an inert gas. For example, in deposition of an oxide, the use of oxygen, which is a main component of the oxide, is preferable in some cases. The baking is preferably performed using a lamp.

Alternatively, treatment for evacuating the inside of the deposition chamber is preferably performed a certain period of time after heated oxygen, a heated inert gas such as a heated rare gas, or the like is introduced to increase a pressure in the deposition chamber. The introduction of the heated gas can desorb the adsorbed substance in the deposition chamber, and the impurities present in the deposition chamber can be reduced. Note that an advantageous effect can be achieved when this treatment is repeated more than or equal to 2 times and less than or equal to 30 times, preferably more than or equal to 5 times and less than or equal to 15 times. Specifically, an inert gas, oxygen, or the like with a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. is introduced to the deposition chamber, so that the pressure therein can be kept to be greater than or equal to 0.1 Pa and less than or equal to 10 kPa, preferably greater than or equal to 1 Pa and less than or equal to 1 kPa, more preferably greater than or equal to 5 Pa and less than or equal to 100 Pa in the time range from 1 minute to 300 minutes, preferably from 5 minutes to 120 minutes. After that, the inside of the deposition chamber is evacuated in the time range from 5 minutes to 300 minutes, preferably from 10 minutes to 120 minutes.

The desorption rate of the adsorbed substance can be further increased also by dummy deposition. Here, the dummy deposition refers to deposition on a dummy substrate by a sputtering method or the like, in which a film is deposited on the dummy substrate and the inner wall of a deposition chamber so that impurities in the deposition chamber and an adsorbed substance on the inner wall of the deposition chamber are confined in the film. As the dummy substrate, a substrate which releases a smaller amount of gas is preferably used. By performing dummy deposition, the concentration of impurities in a film to be formed later can be reduced. Note that the dummy deposition may be performed at the same time as the baking of the deposition chamber.

Next, the details of the transfer chamber 2704 and the load lock chamber 2703 a illustrated in FIG. 58B and the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701 illustrated in FIG. 58C will be described. Note that FIG. 58C illustrates a cross section of the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701.

For the transfer chamber 2704 illustrated in FIG. 58B, the description of the transfer chamber 2704 illustrated in FIG. 58A can be referred to.

The load lock chamber 2703 a includes a substrate delivery stage 2752. When a pressure in the load lock chamber 2703 a becomes atmospheric pressure by being increased from reduced pressure, the substrate delivery stage 2752 receives a substrate from the transfer robot 2763 provided in the atmosphere-side substrate transfer chamber 2702. After that, the load lock chamber 2703 a is evacuated into vacuum so that the pressure therein becomes reduced pressure and then the transfer robot 2763 provided in the transfer chamber 2704 receives the substrate from the substrate delivery stage 2752.

Furthermore, the load lock chamber 2703 a is connected to the vacuum pump 2770 and the cryopump 2771 through valves. For a method for connecting exhaust systems such as the vacuum pump 2770 and the cryopump 2771, the description of the method for connecting the transfer chamber 2704 can be referred to, and the description thereof is omitted here. Note that the unload lock chamber 2703 b illustrated in FIG. 57 can have a structure similar to that of the load lock chamber 2703 a.

The atmosphere-side substrate transfer chamber 2702 includes the transfer robot 2763. The transfer robot 2763 can deliver a substrate from the cassette port 2761 to the load lock chamber 2703 a or deliver a substrate from the load lock chamber 2703 a to the cassette port 2761. Furthermore, a mechanism for suppressing entry of dust or a particle, such as a high-efficiency particulate air (HEPA) filter, may be provided above the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701.

The atmosphere-side substrate supply chamber 2701 includes a plurality of cassette ports 2761. The cassette port 2761 can hold a plurality of substrates.

The surface temperature of the target is set to be lower than or equal to 100° C., preferably lower than or equal to 50° C., more preferably about room temperature (typified by 25° C.). In a sputtering apparatus for a large substrate, a large target is often used. However, it is difficult to form a target for a large substrate without a juncture. In fact, a plurality of targets are arranged so that there is as little space as possible therebetween to obtain a large shape; however, a slight space is inevitably generated. When the surface temperature of the target increases, in some cases, zinc or the like is volatilized from such a slight space and the space might expand gradually. When the space expands, a metal of a backing plate or a metal of a bonding material used for adhesion between the backing plate and the target might be sputtered and might cause an increase in impurity concentration. Thus, it is preferable that the target be cooled sufficiently.

Specifically, to efficiently cool the target, a metal having high conductivity and an excellent heat dissipation property (specifically copper) is used for the backing plate, or a sufficient amount of cooling water is made to flow through a water channel formed in the backing plate.

Note that in the case where the target includes zinc, plasma damage is alleviated by the deposition in an oxygen gas atmosphere; thus, an oxide from which zinc is unlikely to be volatilized can be obtained.

The above-described deposition apparatus enables deposition of an oxide semiconductor whose hydrogen concentration measured by SIMS is lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³, more preferably lower than or equal to 1×10¹⁹ atoms/cm³, still more preferably lower than or equal to 5×10¹⁸ atoms/cm³.

Furthermore, an oxide semiconductor whose nitrogen concentration measured by SIMS is lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 1×10¹⁹ atoms/cm³, more preferably lower than or equal to 5×10¹⁸ atoms/cm³, still more preferably lower than or equal to 1×10¹⁸ atoms/cm³ can be deposited.

Moreover, an oxide semiconductor whose carbon concentration measured by SIMS is lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, more preferably lower than or equal to 1×10¹⁸ atoms/cm³, still more preferably lower than or equal to 5×10¹⁷ atoms/cm³ can be deposited.

Furthermore, an oxide semiconductor can be deposited of which the released amount of each of the following gas molecules (atoms) measured by thermal desorption spectroscopy (TDS) is less than or equal to 1×10¹⁹/cm³, preferably less than or equal to 1×10¹⁸/cm³: a gas molecule (atom) having a mass-to-charge ratio (m/z) of 2 (e.g., a hydrogen molecule), a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18, a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28, and a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44.

With the above deposition apparatus, entry of impurities into the oxide semiconductor can be suppressed. Furthermore, when a film in contact with the oxide semiconductor is formed with the use of the above deposition apparatus, the entry of impurities into the oxide semiconductor from the film in contact therewith can be suppressed.

This embodiment can be implemented in an appropriate combination with any of the structures described in the other embodiments, Example, and the like.

Example

Changes in the electrical characteristics of the transistor 200 when the work functions of the electrode 110_2 a (one of a source electrode and a drain electrode) and the electrode 110_2 b (the other of the source electrode and the drain electrode) vary are examined by calculation.

Calculation of the electrical characteristics is performed with a device simulator Atlas produced by Silvaco Inc. Settings for a transistor 9101 and a transistor 9102 are determined for the calculation. The transistor 9101 has the same structure as the transistor 200. The structure of the transistor 9102 is the same as that of the transistor 200 from which the semiconductor layer 109_2 a 1, the semiconductor layer 109_2 a 2, the semiconductor layer 109_2 b 1, and the semiconductor layer 109_2 b 2 are removed.

<Transistor 9101>

FIG. 60A shows the layered structure of the transistor 9101. The transistor 9101 includes an electrode 9105, an insulating layer 9106, an insulating layer 9107, an insulating layer 9108, a semiconductor layer 9109 a 1, a semiconductor layer 9109 a 2, a semiconductor layer 9109 b 1, a semiconductor layer 9109 b 2, an electrode 9110 a, an electrode 9110 b, a semiconductor layer 9109 c, an insulating layer 9111, and an electrode 9112.

The electrode 9105 corresponds to the electrode 105_2 of the transistor 200. The insulating layer 9106 corresponds to the insulating layer 106 of the transistor 200. The insulating layer 9107 corresponds to the insulating layer 107 of the transistor 200. The insulating layer 9108 corresponds to the insulating layer 108 of the transistor 200. The semiconductor layer 9109 a 1 corresponds to the semiconductor layer 109_2 a 1 of the transistor 200. The semiconductor layer 9109 a 2 corresponds to the semiconductor layer 109_2 a 2 of the transistor 200. The semiconductor layer 9109 b 1 corresponds to the semiconductor layer 109_2 b 1 of the transistor 200. The semiconductor layer 9109 b 2 corresponds to the semiconductor layer 109_2 b 2 of the transistor 200. The electrode 9110 a corresponds to the electrode 110_2 a of the transistor 200. The electrode 9110 b corresponds to the electrode 110_2 b of the transistor 200. The semiconductor layer 9109 c corresponds to the layer 129_2 a, the layer 129_2 b, and the semiconductor layer 109_2 c of the transistor 200. The insulating layer 9111 corresponds to the insulating layer 111_2 of the transistor 200. The electrode 9112 corresponds to the electrode 112_2 of the transistor 200.

Table 1 lists the set values of the transistor 9101 used for calculation of electrical characteristics.

TABLE 1 Setting Channel length L 10 μm Channel width W 0.35 μm Electrode 9112 Work function 5.0 eV (Gate electrode) Thickness 170 nm Insulating layer 9111 Dielectric constant 4.1 Thickness 13 nm Semiconductor layer 9109c Composition IGZO (1:3:2) Electron affinity 4.5 eV Eg 3.5 eV Dielectric constant 15   Electron mobility 0.01 cm²/Vs Hole mobility 0.001 cm²/Vs Nc 5.0E+18 cm³ Nv 1.0E+20 cm³ Thickness 20 nm Electrode 9110a Thickness 50 nm Electrode 9110b Semiconductor layer 9109b1 Composition IGZO (1:1:1) Semiconductor layer 9109b2 Electron affinity 4.7 eV Eg 3.2 eV Dielectric constant 15   Electron mobility 10 cm²/Vs Hole mobility 0.001 cm²/Vs Nc 5.0E+18 cm³ Nv 5.0E+18 cm³ Thickness 15 nm Semiconductor layer 9109a1 Composition IGZO (1:3:2) Semiconductor layer 9109a2 Thickness 5 nm Insulating layer 9108 Material SiON Dielectric constant 4.1 Thickness 5 nm Insulating layer 9107 Material AlOx Dielectric constant 8.1 Thickness 5 nm Insulating layer 9106 Material SiON Dielectric constant 4.1 Thickness 5 nm Electrode 9105 Work function 5.0 eV Thickness 100 nm

The transistor 9101 in which the work functions of the electrode 9110 a and the electrode 9110 b are set to 4.5 eV is referred to as a transistor 9101 a, the transistor 9101 in which the work functions are set to 4.7 eV is referred to as a transistor 9101 b, and the transistor 9101 in which the work functions are set to 4.9 eV is referred to as a transistor 9101 c (see Table 2).

TABLE 2 Work functions of electrodes 9110a and 9110b Transistor 9101a 4.5 eV Transistor 9101b 4.7 eV Transistor 9101c 4.9 eV

Changes in the drain currents (I_(d)) of the transistor 9101 a, the transistor 9101 b, and the transistor 9101 c when the source voltage and the drain voltage are set to 0 V and 1.8 V, respectively, and the gate voltage (V_(g)) is varied from −3 V to 3 V are calculated.

FIGS. 60B and 60C show calculation results. The horizontal axis and the vertical axis of V_(g)-I_(d) curves in FIGS. 60B and 60C represent changes in V_(g) and changes in I_(d), respectively. Note that the vertical axis represents I_(d) on a logarithmic scale. FIG. 60C is a graph obtained by enlarging part of the vertical axis in FIG. 60B.

It is found from FIGS. 60B and 60C that there is no difference between the transistor 9101 a, the transistor 9101 b, and the transistor 9101 c. This means that stable electrical characteristics can be obtained even when the work functions of the electrodes 110_2 a and 110_2 b are changed.

<Transistor 9102>

FIG. 61A shows the layered structure of the transistor 9102. The structure of the transistor 9102 is the same as that of the transistor 9101 from which the semiconductor layer 9109 a 1, the semiconductor layer 9109 a 2, the semiconductor layer 9109 b 1, and the semiconductor layer 9109 b 2 are removed. The set values of the transistor 9102 used for calculation of electrical characteristics are the same as those of the transistor 9101.

The transistor 9102 in which the work functions of the electrodes 9110 a and 9110 b are set to 4.5 eV is referred to as a transistor 9102 a, the transistor 9102 in which the work functions are set to 4.7 eV is referred to as a transistor 9102 b, and the transistor 9102 in which the work functions are set to 4.9 eV is referred to as a transistor 9102 c (see Table 3). The electrical characteristics of the transistor 9102 a, the transistor 9102 b, and the transistor 9102 c are calculated.

TABLE 3 Work functions of electrodes 9110a and 9110b Transistor 9102a 4.5 eV Transistor 9102b 4.7 eV Transistor 9102c 4.9 eV

Changes in the drain currents (I_(d)) of the transistor 9102 a, the transistor 9102 b, and the transistor 9102 c when the source voltage and the drain voltage are set to 0 V and 1.8 V, respectively, and the gate voltage (V_(g)) is varied from −3 V to 3 V are calculated.

FIGS. 61B and 61C show calculation results. The horizontal axis and the vertical axis of V_(g)-I_(d) curves in FIGS. 61B and 61C represent changes in V_(g) and changes in I_(d), respectively. Note that the vertical axis represents I_(d) on a logarithmic scale. FIG. 61C is a graph obtained by enlarging part of the vertical axis in FIG. 61B.

The V_(g)-I_(d) curves of the transistor 9102 a, the transistor 9102 b, and the transistor 9102 c in FIGS. 61B and 61C are different from each other, which indicates that there are differences in electrical characteristics.

<Discussion>

FIG. 62A is an enlarged view of a region 9131 illustrated in FIG. 60A. FIG. 62B illustrates the energy band structure of a portion taken along dashed-dotted line D1-D2 in FIG. 62A. FIG. 62C is an enlarged view of a region 9132 illustrated in FIG. 61A. FIG. 62D illustrates the energy band structure of a portion taken along dashed-dotted line E1-E2 in FIG. 62C. FIG. 62B shows the energies of the conduction band minimums of the electrode 9110 a, the semiconductor layer 9109 b 1, and the semiconductor layer 9109 c. FIG. 62D shows the energies of the conduction band minimums of the electrode 9110 a and the semiconductor layer 9109 c.

The calculation results of the transistor 9101 (the transistor 9101 a, the transistor 9101 b, and the transistor 9101 c) and the transistor 9102 (the transistor 9102 a, the transistor 9102 b, and the transistor 9102 c) suggest that there is a difference in a current path from a source electrode to a channel (a portion of the semiconductor layer 9109 c) between the transistors 9101 and 9102.

The transistor 9101 has a first path, where electrons move from the electrode 9110 a to the semiconductor layer 9109 c; a second path, where electrons move from the electrode 9110 a to the semiconductor layer 9109 c through the semiconductor layer 9109 b 1; and a third path, where electrons move from the electrode 9110 a to the semiconductor layer 9109 c through the semiconductor layer 9109 b 1 and the semiconductor layer 9109 a 1. In contrast, the transistor 9102 has only the first path, where electrons move from the electrode 9110 a to the semiconductor layer 9109 c.

Next, the energy barriers of the first path of the transistor 9102 c and the second path of the transistor 9101 c are considered. In the transistors 9101 c and 9102 c, the work function of the electrode 9110 a is 4.9 eV. The electron affinity of the semiconductor layer 9109 c is 4.5 eV. The electron affinity of the semiconductor layer 9109 b 1 is 4.7 eV. An energy barrier of 0.4 eV is generated between the semiconductor layer 9109 c and the electrode 9110 a.

In the second path, the energy barrier between the electrode 9110 a and the semiconductor layer 9109 b 1 is 0.2 eV, and the energy barrier between the semiconductor layer 9109 b 1 and the semiconductor layer 9109 c is 0.2 eV (see FIG. 62B).

In the first path, the energy barrier between the electrode 9110 a and the semiconductor layer 9109 c is 0.4 eV (see FIG. 62D).

A smaller energy barrier allows electrons to move more easily. Thus, electrons move more easily in the second path, where the energy barrier changes stepwise, than in the first path. In general, the work functions of even the same metal materials are likely to vary because of the deposition condition, the crystal orientation, and the like. When the work function of the source electrode varies, the amount of electrons that move from the source electrode to the channel (the amount of current) is likely to vary. That is to say, the electrical characteristics of a transistor are likely to noticeably vary. However, when the height of the energy barrier is small, an influence of variation in the work function can also be small. The height of the energy barrier is preferably 0.3 eV or less, more preferably 0.2 eV or less.

Providing the semiconductor layer 9109 b 1 such that it overlaps with the electrode 9110 a enables fabrication of a transistor with favorable electrical characteristics and a transistor with small variation in electrical characteristics.

This application is based on Japanese Patent Application serial no. 2016-028115 filed with Japan Patent Office on Feb. 17, 2016 and Japanese Patent Application serial no. 2016-028117 filed with Japan Patent Office on Feb. 17, 2016, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first transistor; a second transistor; and a first insulating layer, wherein the first transistor comprises a first electrode, a second electrode, a third electrode, a fourth electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first layer, and a second layer, and a second insulating layer, wherein the second transistor comprises a fifth electrode, a sixth electrode, a seventh electrode, an eighth electrode, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer, a seventh semiconductor layer, an eighth semiconductor layer, a third layer, a fourth layer, and a third insulating layer, wherein the first insulating layer comprises a region overlapping with the first electrode, wherein the first semiconductor layer comprises a region overlapping with the first insulating layer, wherein the second semiconductor layer comprises a region overlapping with the first semiconductor layer, wherein the second semiconductor layer comprises a region overlapping with the second electrode and a region overlapping with the third electrode, wherein the first layer comprises a region overlapping with the second electrode, wherein the second layer comprises a region overlapping with the third electrode, wherein the third semiconductor layer comprises a region overlapping with the second semiconductor layer, wherein the second insulating layer comprises a region overlapping with the third semiconductor layer, wherein the fourth electrode comprises a region overlapping with the second insulating layer, wherein a side surface of the fourth electrode and the third semiconductor layer partly overlap with each other with the second insulating layer therebetween, wherein the first electrode and the fourth electrode partly overlap with each other with the second semiconductor layer therebetween, wherein the first insulating layer comprises a region overlapping with the fifth electrode, wherein the fourth semiconductor layer comprises a region overlapping with the first insulating layer, wherein the sixth semiconductor layer comprises a region overlapping with the fourth semiconductor layer, wherein the sixth electrode comprises a region overlapping with the sixth semiconductor layer, wherein the third layer comprises a region overlapping with the sixth electrode, wherein the fifth semiconductor layer comprises a region overlapping with the first insulating layer, wherein the seventh semiconductor layer comprises a region overlapping with the fifth semiconductor layer, wherein the seventh electrode comprises a region overlapping with the seventh semiconductor layer, wherein the fourth layer comprises a region overlapping with the seventh electrode, wherein the eighth semiconductor layer comprises a region overlapping with the sixth semiconductor layer and a region overlapping with the seventh semiconductor layer, wherein the third insulating layer comprises a region overlapping with the eighth semiconductor layer, wherein the eighth electrode comprises a region overlapping with the third insulating layer, wherein a side surface of the eighth electrode and the eighth semiconductor layer partly overlap with each other with the third insulating layer therebetween, and wherein the fifth electrode and the eighth electrode partly overlap with each other with the eighth semiconductor layer therebetween.
 2. The semiconductor device according to claim 1, wherein the first to eighth semiconductor layers each comprise an oxide semiconductor.
 3. The semiconductor device according to claim 1, wherein the first to fourth layers each comprise an oxide semiconductor.
 4. The semiconductor device according to claim 1, wherein at least one of the first electrode and the fourth electrode is capable of functioning as a gate electrode.
 5. The semiconductor device according to claim 1, wherein at least one of the fifth electrode and the eighth electrode is capable of functioning as a gate electrode.
 6. The semiconductor device according to claim 1, wherein a channel is formed in the second semiconductor layer.
 7. The semiconductor device according to claim 1, wherein a channel is formed in the eighth semiconductor layer.
 8. The semiconductor device according to claim 1, wherein a threshold voltage of the second transistor when the fifth electrode and the eighth electrode have a same potential is higher than a threshold voltage of the first transistor when the first electrode and the fourth electrode have a same potential.
 9. An electronic device comprising: the semiconductor device according to claim 1; and an antenna, a battery, an operation switch, a microphone, or a speaker.
 10. A semiconductor wafer comprising: more than one semiconductor device according to claim 1; and a separation region defining each of the semiconductor devices.
 11. A semiconductor device comprising: a first transistor; and a first insulating layer comprising a first opening, the first insulating layer partly overlapping with and surrounding the first transistor, wherein the first transistor comprises: a pair of first oxide semiconductor layers each having an inner side surface facing each other; a first electrode over one of the pair of first oxide semiconductor layers; a second electrode over the other of the pair of first oxide semiconductor layers; a second oxide semiconductor layer in contact with the inner side surfaces of the pair of first oxide semiconductor layers; a first gate insulating layer over the second oxide semiconductor layer; and a first gate electrode over the first gate insulating layer, wherein the second oxide semiconductor layer is in contact with an inner wall of the first opening, and wherein at least part of the first gate insulating layer and part of the first gate electrode are each in the first opening.
 12. The semiconductor device according to claim 11, wherein a bandgap of the second oxide semiconductor layer is larger than a bandgap of the pair of first oxide semiconductor layers.
 13. The semiconductor device according to claim 11, wherein the first transistor comprises a third oxide semiconductor layer under and in contact with the pair of first oxide semiconductor layers.
 14. The semiconductor device according to claim 13, wherein the second oxide semiconductor layer is in contact with an upper surface of the third oxide semiconductor layer.
 15. The semiconductor device according to claim 11, wherein the first transistor comprises a pair of third oxide semiconductor layers under the pair of first oxide semiconductor layers, wherein the pair of third oxide semiconductor layers each have a side surface facing each other, and wherein the second oxide semiconductor layer is in contact with the inner side surfaces of the pair of third oxide semiconductor layers.
 16. The semiconductor device according to claim 11, comprising a second transistor, wherein the first insulating layer comprises a second opening and partly overlaps with and surrounds the second transistor, wherein the second transistor comprises: a fourth oxide semiconductor layer; a third electrode and a fourth electrode over the fourth oxide semiconductor layer, the third electrode and the fourth electrode have side surfaces facing each other; a fifth oxide semiconductor layer in contact with the side surfaces of the third electrode and the fourth electrode, an upper surface of the fourth oxide semiconductor layer, and an inner wall of the second opening; a second gate insulating layer over the fifth oxide semiconductor layer; and a second gate electrode over the second gate insulating layer, and wherein at least part of the second gate insulating layer and part of the second gate electrode are each in the second opening.
 17. The semiconductor device according to claim 16, wherein a bandgap of the second oxide semiconductor layer and a bandgap of the fifth oxide semiconductor layer are each larger than a bandgap of the pair of first oxide semiconductor layers and a bandgap of the fourth oxide semiconductor layer.
 18. The semiconductor device according to claim 16, wherein the second transistor comprises: a third gate insulating layer below the fourth oxide semiconductor layer; and a third gate electrode below the third gate insulating layer.
 19. The semiconductor device according to claim 18, wherein one of the first electrode and the second electrode is electrically connected to the first gate electrode and the third gate electrode.
 20. The semiconductor device according to claim 16, wherein each of the pair of first oxide semiconductor layers, the second oxide semiconductor layer, the fourth oxide semiconductor layer, and the fifth oxide semiconductor layer comprises indium, gallium, and zinc. 